DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7,9,11-14 and 16 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tomura et al (US 2023/0230844).
Regarding claims 1 and 5-6, Tomura et al disclose a process comprising placing a substrate in a plasma processing chamber for etching a silicon -containing film (SF) [0068], wherein the silicon-containing film include a silicon oxide film, a silicon nitride film [0063] and such SF reads on the claimed “dielectric layer” and a mask film (MF) comprises metal-containing, such as tungsten is adjacent to the dielectric film to be selectively etched ([0064] and Figures 3-4);and aforesaid metal-containing film reads on the claimed “conductive layer” over a semiconductor substrate (UF) [0062].
Tomura et al disclose that after the substrate is placed in the etching chamber, the substrate temperature is adjusted to a set temperature and the set temperature may be, for example, 20° C. or lower, 0° C. or lower. −10° C. or lower, −20° C. or lower, −30° C. or lower, −40° C. or lower, −50° C. or lower, −60° C. or lower, or −70° C. or lower [0069] and aforesaid inherently teach the limitation of whole performing the etching process, cooling the workpiece to a processing temperature that is below an ambient temperature because typically, ambient temperature is the room temperature or atmospheric temperature; typically ranging from to 15-24 degree C (source:Google).
Regarding claims 2-3 and 7, Tomura et al disclose that forming a plasma etchant from a process gas contains hydrogen fluoride (HF) in order to selectively etch the silicon -containing film (dielectric layer) ([0070], [0071] and Figure 4).
Regarding claim 4, Tomura et al disclose that the plasma processing apparatus using any plasma source, such as an inductively coupled plasma source [0131].
Regarding claim 9, Tomura et al disclose above that during the processing in step ST12 (first etching), the temperature of the substrate support 11 is maintained at the set temperature reached by the adjustment in step ST11 (Figure 2), wherein the set temperature is cooling the substrate below 20 degree C [0069],[0070]; and aforesaid teaching inherently teach the cooling causes the etching selectivity towards to the dielectric layer relative to the conductive layer to increase.
Regarding claims 11-12, Tomura et al disclose that the mask film (MF) comprises metal-containing, such as tungsten is adjacent to the dielectric film to be selectively etched ([0064] and Figures 3-4); and aforesaid metal-containing film reads on the claimed “conductive layer”.
Regarding claim 13, Tomura et al disclose a process comprising placing a substrate in a plasma processing chamber for etching a silicon -containing film (SF) [0068], wherein the silicon-containing film include a silicon oxide film, a silicon nitride film [0063] and such SF reads on the claimed “dielectric layer” and a mask film (MF) comprises metal-containing, such as tungsten is adjacent to the dielectric film to be selectively etched ([0064] and Figures 3-4);and aforesaid metal-containing film reads on the claimed “conductive layer” over a semiconductor substrate (UF) [0062].
Tomura et al disclose that after the substrate is placed in the etching chamber, the substrate temperature is adjusted to a set temperature and the set temperature may be, for example, 20° C. or lower, 0° C. or lower. −10° C. or lower, −20° C. or lower, −30° C. or lower, −40° C. or lower, −50° C. or lower, −60° C. or lower, or −70° C. or lower [0069] and aforesaid inherently teach the limitation of whole performing the etching process, cooling the workpiece to a processing temperature that is below an ambient temperature because typically, ambient temperature is the room temperature or atmospheric temperature; typically ranging from to 15-24 degree C (source:Google).
Tomura et al disclose above that during the processing in step ST12 (first etching), the temperature of the substrate support 11 is maintained at the set temperature reached by the adjustment in step ST11 (Figure 2), wherein the set temperature is cooling the substrate below 20 degree C [0069],[0070]; and aforesaid teach easily reads on the claimed first etching selectivity towards the dielectric layer relative to the conductive layer.
Tomura et al also disclose that performing a second etching (ST13) and in one example, the temperature of the substrate W in step ST12 (first etching) (TL2) may be −40° C., and the temperature of the substrate W in step ST13 (second etching) (TH2) may be 0° C ([0106] and Figure 2);and aforesaid teaching inherently teach the cooling causes the plasma etchant to exhibit a second etching selectivity towards to the dielectric layer relative to the conductive layer, the second etching selectivity being greater than the first etching selectivity.
Regarding claim 14, Tomura et al disclose that the plasma processing apparatus using any plasma source, such as an inductively coupled plasma source [0131].
Regarding claim 16, Tomura et al disclose above that the processing temperature is greater than or equal to -10 and less than 20 degree C [0069].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8,15,17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomura et al (US 2023/0230844) as applied to claims 1,7 and 13 above.
Regarding claim 8, Tomura et al disclose above f or the claims 1 and 7 (see above) but fail to teach the ion energy of the plasma etchant is adjusting to the specified value as the context of claim 8.
However, Tomura et al disclose that when the second etching is started, the processing conditions for etching are changed from those in step ST12 (recipe 1) to those in step ST13 (recipe 2). In other words, in step ST13, the silicon-containing film SF is etched using a recipe different from the recipe in step ST12. The recipe change may include using the second process gas different from the first process gas, performing a temperature control process to increase the temperature of the substrate W higher than in step ST12, or both the processes [0099].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the ion energy of the plasma etchant as suggested by Tomura et al.
Furthermore, in the absence of evidence indicating that said value is critical, one of ordinary skill on the art would have been easily motivated to optimize such for predictable result as the general processing conditions are similar in nature.
Regarding claim 15, similar analysis applies like claim 8 (see above). Additionally, Tomura et al disclose that upon the shift from step ST12 to step ST13, (II) the DC voltage supplied to the ESC 1111 (ESC voltage) may be reduced to reduce the attracting force of the ESC 1111 [0106] and aforesaid teaching easily reads on the limitation of adjusting ion energy of the plasma etchant because DC voltage supplied to the substrate has effect on the substrate to be etched as suggested by Tomura et al.
Regarding claim 17, Tomura et al disclose that the dielectric layer is defined by a width and height (see Figures 3-4) and the claimed ratio of the height to width would broadly encompasses the claimed range.
Regarding claim 18, Tomura et al disclose a process comprising placing a substrate in a plasma processing chamber for etching a silicon -containing film (SF) [0068], wherein the silicon-containing film include a silicon oxide film, a silicon nitride film [0063] and such SF reads on the claimed “dielectric layer” and a mask film (MF) comprises metal-containing, such as tungsten is adjacent to the dielectric film to be selectively etched ([0064] and Figures 3-4);and aforesaid metal-containing film reads on the claimed “conductive layer” over a semiconductor substrate (UF) [0062].
Tomura et al disclose that after the substrate is placed in the etching chamber, the substrate temperature is adjusted to a set temperature and the set temperature may be, for example, 20° C. or lower, 0° C. or lower. −10° C. or lower, −20° C. or lower, −30° C. or lower, −40° C. or lower, −50° C. or lower, −60° C. or lower, or −70° C. or lower [0069] and aforesaid inherently teach the limitation of whole performing the etching process, cooling the workpiece to a processing temperature that is below an ambient temperature because typically, ambient temperature is the room temperature or atmospheric temperature; typically ranging from to 15-24 degree C (source: Google).
Tomura et al disclose above that during the processing in step ST12 (first etching), the temperature of the substrate support 11 is maintained at the set temperature reached by the adjustment in step ST11 (Figure 2), wherein the set temperature is cooling the substrate below 20 degree C [0069],[0070]; and aforesaid teach easily reads on the claimed first etching selectivity towards the dielectric layer relative to the conductive layer.
Tomura et al also disclose that performing a second etching (ST13) and in one example, the temperature of the substrate W in step ST12 (first etching) (TL2) may be −40° C., and the temperature of the substrate W in step ST13 (second etching) (TH2) may be 0° C ([0106] and Figure 2);and aforesaid teaching inherently teach the cooling causes the plasma etchant to exhibit a second etching selectivity towards to the dielectric layer relative to the conductive layer, the second etching selectivity being greater than the first etching selectivity.
Tomura et al also disclose that upon the shift from step ST12 (First etching) to step ST13 (second etching), (II) the DC voltage supplied to the ESC 1111 (ESC voltage) may be reduced to reduce the attracting force of the ESC 1111 [0106].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to appreciate that such adjustment to the DC voltage applied to the substrate has effect on the ion energy for reducing attracting force of ions as suggested by Tamura et al.
Regarding claim 19, Tomura et al disclose that forming a plasma etchant from a process gas contains hydrogen fluoride (HF) [0070]; Tomura et al disclose that the plasma processing apparatus using any plasma source, such as an inductively coupled plasma source [0131].
Regarding claim 20, Tomura et al disclose above that the processing temperature is greater than or equal to -10 and less than 20 degree C [0069].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomura et al (US 2023/0230844) as applied to claim 1 above, and further in view of Dieny et al (US 2017/0309497).
Tomura et al disclose above for claim 1 but fail to disclose the dielectric layer comprises a low-k dielectric material.
However, in the same field of endeavor, Dieny et al disclose a process of selectively etching dielectric layer 103, with respect to a conductive material 110’ [0128], wherein the dielectric layer 103 may be constituted of a silicon oxide (SiO.sub.2, SiOCH), a silicon nitride (Si.sub.3N.sub.4, SiCN) or an insulating polymer material (e.g. materials sold by the “Dow Chemical” company under the designation “SILK” and by the “Honeywell” company under the designation “FLARE”) [0124], aforesaid SiLK™ (a trademark of The Dow Chemical Company) is a well-known low- organic polymer dielectric (source: Google).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ Dieny et al al's teaching of using dielectric material as silicon oxide, silicon nitride or Silk (low-k dielectric material) into the teaching of Tomura et al because they are functionally equivalent as taught by Dieny et al.
Conclusion
The prior art made of record, listed 892 and not relied upon is considered pertinent to applicant's disclosure.
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SHAMIM AHMED
Primary Examiner
Art Unit 1713
/SHAMIM AHMED/ Primary Examiner, Art Unit 1713