CTFR 18/424,262 CTFR 75030 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20, as to the point that the applied prior art, Tomura fails to teach reducing a temperature below the ambient temperature, while the dielectric layer being etched , have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 07-103 AIA The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. 07-21-aia AIA Claim (s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tomura et al (US 2023/0230844) in view of Leung et al (US 2003/0235993) . Regarding claims 1 and 13, Tomura et al disclose a process comprising placing a substrate in a plasma processing chamber for etching a silicon -containing film (SF) [0068], wherein the silicon-containing film include a silicon oxide film , a silicon nitride film [0063] and such SF reads on the claimed “dielectric layer” and a mask film (MF) comprises metal-containing , such as tungsten is adjacent to the dielectric film to be selectively etched ([0064] and Figures 3-4);and aforesaid metal-containing film reads on the claimed “conductive layer” over a semiconductor substrate (UF) [0062]. Tomura et al disclose that after the substrate is placed in the etching chamber, the substrate temperature is adjusted to a set temperature and the set temperature may be, for example, 20° C. or lower , 0° C. or lower. −10° C. or lower, −20° C. or lower, −30° C. or lower, −40° C. or lower, −50° C. or lower, −60° C. or lower, or −70° C. or lower [0069]. Unlike the instant invention, Tomura et al fail to explicitly disclose that the temperature is reduced to a temperature below the ambient temperature, while the dielectric layer being etched . However, in the same field of endeavor, Leung et al disclose selective etching low-k dielectric layer may be in presence of conductive material [0003],[0006], wherein the wafer (substrate) is maintained at a temperature sufficiently high to volatilize most of the etch products, and sufficiently low so that a layer of passivating deposits and etch product deposits is retained on the sidewalls 105 of freshly etched feature 101 . Typically, the substrate 150 is kept at a temperature of about 15.degree. C . [0035]; and aforesaid temperature of about 15 degree C is below the ambient temperature. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ Leung et al's teaching of maintaining the temperature at about 15 degree C (below ambient temperature) into the teaching of Tomura et al for protecting or passivating deposits and etch product deposits is retained on the sidewalls 105 of freshly etched feature , as suggested by Leung et al. By doing so, one of ordinary skill in the art would maintain the etched feature’s profile uniformity. Regarding claims 2-3 and 7, Tomura et al disclose that forming a plasma etchant from a process gas contains hydrogen fluoride (HF) in order to selectively etch the silicon -containing film (dielectric layer) ([0070], [0071] and Figure 4). Regarding claim 4, Tomura et al disclose that the plasma processing apparatus using any plasma source, such as an inductively coupled plasma source [0131]. Regarding claim 5, Leung et al disclose above that typically, the substrate 150 is kept at a temperature of about 15.degree. C . [0035]; and aforesaid temperature of about 15 degree C is below the ambient temperature and overlaps the claimed range of greater than or equal to -50 degree C and less than 20 degree C; and overlapping ranges are prima facie obvious, MPEP 2144.05. Regarding claim 6, Tomura et al is focusing a selective etching of dielectric layer in a very low temperature as a setting temperature for example, 20° C. or lower, 0° C. or lower. −10° C. or lower, −20° C. or lower, −30° C. or lower, −40° C. or lower, −50° C. or lower, −60° C. or lower, or −70° C. or lower [0069] but fail to disclose reducing a temperature while etching the dielectric layer to the claimed range. However, Leung et al disclose selective etching low-k dielectric layer may be in presence of conductive material [0003],[0006], wherein the wafer (substrate) is maintained at a temperature sufficiently high to volatilize most of the etch products, and sufficiently low so that a layer of passivating deposits and etch product deposits is retained on the sidewalls 105 of freshly etched feature 101 . Typically, the substrate 150 is kept at a temperature of about 15.degree. C. [0035]; and one of ordinary skill in the art can optimize for predictable result without showing any criticality of the claimed range. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to achieve the claimed lower temperature range of greater than or equal to -20 degree C to approximately -10 degree C by cooling or reducing as suggested by Leong et al. Regarding claim 8, Tomura et al disclose above for the claims 1 and 7 (see above) but fail to teach the ion energy of the plasma etchant is adjusting to the specified value as the context of claim 8. However, Tomura et al disclose that when the second etching is started, the processing conditions for etching are changed from those in step ST12 (recipe 1) to those in step ST13 (recipe 2). In other words, in step ST13, the silicon-containing film SF is etched using a recipe different from the recipe in step ST12. The recipe change may include using the second process gas different from the first process gas, performing a temperature control process to increase the temperature of the substrate W higher than in step ST12, or both the processes [0099]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the ion energy of the plasma etchant as suggested by Tomura et al. Furthermore, in the absence of evidence indicating that said value is critical, one of ordinary skill on the art would have been easily motivated to optimize such for predictable result as the general processing conditions are similar in nature. Regarding claim 9, Leung et al disclose selective etching low-k dielectric layer may be in presence of conductive material [0003],[0006], wherein the wafer (substrate) is maintained at a temperature sufficiently high to volatilize most of the etch products, and sufficiently low so that a layer of passivating deposits and etch product deposits is retained on the sidewalls 105 of freshly etched feature 101 . Typically, the substrate 150 is kept at a temperature of about 15.degree. C. using a flow of helium on the backside of the substrate 150 [0035]; and aforesaid teaching obviously teach the cooling causes the etching selectivity towards to the dielectric layer relative to the conductive layer to increase. Regarding claim 10, Leung et al disclose selective etching low-k dielectric layer may be in presence of conductive material [0003],[0006]. Regarding claims 11-12, Tomura et al disclose that the mask film (MF) comprises metal-containing, such as tungsten is adjacent to the dielectric film to be selectively etched ([0064] and Figures 3-4); and aforesaid metal-containing film reads on the claimed “conductive layer”. Regarding claim 14, Tomura et al disclose that the plasma processing apparatus using any plasma source, such as an inductively coupled plasma source [0131]. Regarding claim 15, similar analysis applies like claim 8 (see above). Additionally, Tomura et al disclose that upon the shift from step ST12 to step ST13, (II) the DC voltage supplied to the ESC 1111 (ESC voltage) may be reduced to reduce the attracting force of the ESC 1111 [0106] and aforesaid teaching easily reads on the limitation of adjusting ion energy of the plasma etchant because DC voltage supplied to the substrate has effect on the substrate to be etched as suggested by Tomura et al. Regarding claim 16, Leung et al disclose above that typically, the substrate 150 is kept at a temperature of about 15.degree. C . [0035]; and aforesaid temperature of about 15 degree C is below the ambient temperature and overlaps the claimed range of greater than or equal to -10 degree C and less than 20 degree C; and overlapping ranges are prima facie obvious, MPEP 2144.05. Regarding claim 17, Tomura et al disclose that the dielectric layer is defined by a width and height (see Figures 3-4) and the claimed ratio of the height to width would broadly encompasses the claimed range. Regarding claim 18, Tomura et al disclose a process comprising placing a substrate in a plasma processing chamber for etching a silicon -containing film (SF) [0068], wherein the silicon-containing film include a silicon oxide film, a silicon nitride film [0063] and such SF reads on the claimed “dielectric layer” and a mask film (MF) comprises metal-containing, such as tungsten is adjacent to the dielectric film to be selectively etched ([0064] and Figures 3-4);and aforesaid metal-containing film reads on the claimed “conductive layer” over a semiconductor substrate (UF) [0062]. Tomura et al disclose that after the substrate is placed in the etching chamber, the substrate temperature is adjusted to a set temperature and the set temperature may be, for example, 20° C. or lower, 0° C. or lower. −10° C. or lower, −20° C. or lower, −30° C. or lower, −40° C. or lower, −50° C. or lower, −60° C. or lower, or −70° C. or lower [0069]. Unlike the instant invention, Tomura et al fail to explicitly disclose that the temperature is reduced to a temperature below the ambient temperature, while the dielectric layer being etched . However, in the same field of endeavor, Leung et al disclose selective etching low-k dielectric layer may be in presence of conductive material [0003],[0006], wherein the wafer (substrate) is maintained at a temperature sufficiently high to volatilize most of the etch products, and sufficiently low so that a layer of passivating deposits and etch product deposits is retained on the sidewalls 105 of freshly etched feature 101 . Typically, the substrate 150 is kept at a temperature of about 15.degree. C . [0035]; and aforesaid temperature of about 15 degree C is below the ambient temperature. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ Leung et al's teaching of maintaining the temperature at about 15 degree C (below ambient temperature) into the teaching of Tomura et al for protecting or passivating deposits and etch product deposits is retained on the sidewalls 105 of freshly etched feature , as suggested by Leung et al. Tomura et al disclose above that during the processing in step ST12 (first etching), the temperature of the substrate support 11 is maintained at the set temperature reached by the adjustment in step ST11 (Figure 2), wherein the set temperature is cooling the substrate below 20 degree C [0069],[0070]; and aforesaid teach easily reads on the claimed first etching selectivity towards the dielectric layer relative to the conductive layer. Modified Tomura et al also disclose above that cooling or reducing temperature while etching the dielectric layer; and aforesaid teaching obviously teach the cooling causes the plasma etchant to exhibit a second etching selectivity towards to the dielectric layer relative to the conductive layer, the second etching selectivity being greater than the first etching selectivity. Tomura et al also disclose that upon the shift from step ST12 (First etching) to step ST13 (second etching), (II) the DC voltage supplied to the ESC 1111 (ESC voltage) may be reduced to reduce the attracting force of the ESC 1111 [0106] . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to appreciate that such adjustment to the DC voltage applied to the substrate has effect on the ion energy for reducing attracting force of ions as suggested by Tamura et al. Regarding claim 19, Tomura et al disclose that forming a plasma etchant from a process gas contains hydrogen fluoride (HF) [0070]; Tomura et al disclose that the plasma processing apparatus using any plasma source, such as an inductively coupled plasma source [0131]. Regarding claim 20, Leung et al disclose above that typically, the substrate 150 is kept at a temperature of about 15.degree. C . [0035]; and aforesaid temperature of about 15 degree C is below the ambient temperature and overlaps the claimed range of greater than or equal to -10 degree C and less than 20 degree C; and overlapping ranges are prima facie obvious, MPEP 2144.05 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bergman et al (US 2019/0019688) disclose selective etching dielectric layer, wherein the etch process may be quenched by application of a diluent or other material that may perform one or more actions of diluting the etchant, and/or reducing a temperature of the etchant [0038] . Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAMIM AHMED whose telephone number is (571)272-1457. The examiner can normally be reached M-TH (8-5:30pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Allen can be reached at 571-270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. SHAMIM AHMED Primary Examiner Art Unit 1713 /SHAMIM AHMED/ Primary Examiner, Art Unit 1713 Application/Control Number: 18/424,262 Page 2 Art Unit: 1713 Application/Control Number: 18/424,262 Page 3 Art Unit: 1713 Application/Control Number: 18/424,262 Page 4 Art Unit: 1713 Application/Control Number: 18/424,262 Page 5 Art Unit: 1713 Application/Control Number: 18/424,262 Page 6 Art Unit: 1713 Application/Control Number: 18/424,262 Page 7 Art Unit: 1713 Application/Control Number: 18/424,262 Page 8 Art Unit: 1713 Application/Control Number: 18/424,262 Page 9 Art Unit: 1713 Application/Control Number: 18/424,262 Page 10 Art Unit: 1713 Application/Control Number: 18/424,262 Page 11 Art Unit: 1713
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