DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 05/25/2026. Claims 1-16 and 21-24 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 01/29/2024 is acceptable.
Election/Restrictions
Applicant’s election, without traverse invention II, Species IV with claims 1-16 and 21-24, in the “Response to Election / Restriction Filed” filed on 05/25/2026 is acknowledged. This office action considers claims 1-16 and 21-24 are thus pending for prosecution.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 11 and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US 10,395,974 A1; hereafter Chou) in view of Yonchara et al (US 6468,923 A1; hereafter Yonchara).
PNG
media_image1.png
305
518
media_image1.png
Greyscale
Regarding claim 1. Chou discloses a method of forming a semiconductor (Fig [8-21]) structure, comprising:
forming a second epitaxial semiconductor layer (Fig [8-21], etch stop layer 1002, col 10, lines 10-55) over a first epitaxial semiconductor layer (buffer layer 904, col 9, lines 10-55) that is located on a first substrate (Fig [8-21], sacrificial substrate 902, col 9, lines 10-55),
forming a first dielectric capping layer (Fig [8-21], insulating layer 106b, col 12, lines 1-35) over the second epitaxial semiconductor layer (etch stop layer 1002);
bonding the first dielectric capping layer (Fig [8-21], insulating layer 106b, col 12, lines 1-35) to a second dielectric capping layer (Fig [8-21], insulating layer 106a col 8, lines 50-68) located on a second substrate (Fig 13, handle substrate 104, col 3, lines 30-55); and
removing the first substrate (Fig [8-21], sacrificial substrate 902, col 9, lines 10-55) to provide a semiconductor-on-insulator (SOI) structure ( Fig 13-15, removed sacrificial substrate 902) comprising the first epitaxial semiconductor layer (buffer layer 904, col 9, lines 10-55) and the second epitaxial semiconductor layer (etch stop layer 1002) on the second substrate (Fig 13, handle substrate 104, col 3, lines 30-55), and a buried insulator layer ( insulating layers [106a, 106b]) comprising the first dielectric capping layer (Fig [8-21], insulating layer 106b, col 12, lines 1-35) and the second dielectric capping layer (Fig [8-21], insulating layer 106a,col 8, lines 50-68) located between the second epitaxial semiconductor layer (Fig [8-21], etch stop layer 1002, col 10, lines 10-55) and the second substrate (Fig 13, handle substrate 104, col 3, lines 30-55).
But Chou does not disclose explicitly wherein a second resistivity of the second epitaxial semiconductor layer is different than a first resistivity of the first epitaxial semiconductor layer.
In a similar field of endeavor, Yonchara discloses wherein a second resistivity of the second epitaxial semiconductor layer is different than a first resistivity of the first epitaxial semiconductor layer ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou in light of Yonchara teaching “wherein a second resistivity of the second epitaxial semiconductor layer is different than a first resistivity of the first epitaxial semiconductor layer ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45)” for further advantage such as produces semiconductor wafers having efficient and low defects.
Regarding claim 2. Chou and Yonchara discloses the method of claim 1, But Chou does not disclose explicitly wherein the second resistivity of the second epitaxial semiconductor layer is greater than the first resistivity of the first epitaxial semiconductor layer.
In a similar field of endeavor, Yonchara discloses wherein the second resistivity of the second epitaxial semiconductor layer is greater than the first resistivity of the first epitaxial semiconductor layer ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45. Therefore, second resistivity of the second epitaxial semiconductor layer can greater than the first resistivity of the first epitaxial semiconductor layer).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou in light of Yonchara teaching “wherein the second resistivity of the second epitaxial semiconductor layer is greater than the first resistivity of the first epitaxial semiconductor layer ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45. Therefore, second resistivity of the second epitaxial semiconductor layer can greater than the first resistivity of the first epitaxial semiconductor layer)” for further advantage such as produces semiconductor wafers having efficient and low defects.
Regarding claim 3. Chou and Yonchara discloses the method of claim 2, Yonchara discloses wherein the second resistivity of the second epitaxial semiconductor layer is greater than the first resistivity of the first epitaxial semiconductor layer by a factor of at least two ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45. Therefore, second resistivity of the second epitaxial semiconductor layer can greater than the first resistivity of the first epitaxial semiconductor layer by a factor of at least two).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou in light of Yonchara teaching “wherein the second resistivity of the second epitaxial semiconductor layer is greater than the first resistivity of the first epitaxial semiconductor layer by a factor of at least two ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45. Therefore, second resistivity of the second epitaxial semiconductor layer can greater than the first resistivity of the first epitaxial semiconductor layer by a factor of at least two)” for further advantage such as produces semiconductor wafers having efficient and low defects.
Regarding claim 4. Chou and Yonchara discloses the method of claim 3, Yonchara discloses wherein the second resistivity of the second epitaxial semiconductor layer is greater than the first resistivity of the first epitaxial semiconductor layer by a factor of ten or more ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45. Therefore, the second resistivity of the second epitaxial semiconductor layer can greater than the first resistivity of the first epitaxial semiconductor layer by a factor of ten or more).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou in light of Yonchara teaching “wherein the second resistivity of the second epitaxial semiconductor layer is greater than the first resistivity of the first epitaxial semiconductor layer by a factor of ten or more ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45. Therefore, the second resistivity of the second epitaxial semiconductor layer can greater than the first resistivity of the first epitaxial semiconductor layer by a factor of ten or more)” for further advantage such as produces semiconductor wafers having efficient and low defects.
Regarding claim 5. Chou and Yonchara discloses the method of claim 1, Chou further discloses wherein the first substrate comprises a crystalline semiconductor material (Fig [8-21], Col 9, lines 10-25, “In some embodiments, the sacrificial substrate 902 is a bulk semiconductor substrate and/or comprises, for example, monocrystalline silicon”), and the first epitaxial semiconductor layer (Fig [8-21], buffer layer 904) comprises a crystalline semiconductor material ( buffer layer 904 is or comprises monocrystalline silicon, col 9, lines 20-55) formed on the crystalline semiconductor material of the first substrate (Fig [8-21], sacrificial substrate 902) by molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) ( col 9, lines 40-55).
Regarding claim 6. Chou and Yonchara discloses the method of claim 1, Chou further discloses wherein the first substrate (Fig [8-21], sacrificial substrate 902, col 9, lines 10-55) comprises a semiconductor material that is doped with dopants of a first conductivity-type at a first doping concentration (col 9, lines 10-50), and the first epitaxial semiconductor layer (Fig [8-21], buffer layer 904, col 9, lines 10-55) is doped with dopants of the first conductivity-type at a second doping concentration that is less than the first doping concentration (col 9, lines 10-50).
Regarding claim 7. Chou and Yonchara discloses the method of claim 1, Chou further discloses wherein removing the first substrate comprises:
performing a thinning process to remove a first portion of the first substrate (sacrificial substrate 902, Fig [14-16], col 12, lines 40-68, col 13, lines 1-10); and performing an etching process to remove a remaining portion of the first substrate using an etching chemistry having a higher etch selectivity for the first substrate (sacrificial substrate 902, Fig [14-16], col 12, lines 40-68, col 13, lines 1-10) than for the first epitaxial semiconductor layer ( Fig [14-16], buffer layer 904, col 12, lines 40-68, col 13, lines 1-10).
Regarding claim 11. Chou and Yonchara discloses the method of claim 1, Chou further discloses further comprising:
forming a third epitaxial semiconductor layer (Fig [8-21], device layer 108 are formed by epitaxy, col 10, lines 55-68) over the first epitaxial semiconductor layer (buffer layer 904, col 9, lines 10-55).
Regarding claim 13. Chou discloses a method of forming a semiconductor structure, comprising:
forming a second epitaxial semiconductor layer (Fig [8-21], etch stop layer 1002, col 10, lines 10-55) over a first epitaxial semiconductor layer (Fig [8-21], buffer layer 904, col 9, lines 10-55) that is located on a first substrate (Fig [8-21], sacrificial substrate 902, col 9, lines 10-55);
forming a first dielectric capping layer (Fig [8-21], insulating layer 106b, col 12, lines 1-35) over the second epitaxial semiconductor layer (Fig [8-21], etch stop layer 1002, col 10, lines 10-55);
bonding the first dielectric capping layer (Fig [8-21], insulating layer 106b, col 12, lines 1-35) to a second dielectric capping layer (Fig [8-21], insulating layer 106a) located on a second substrate (Fig 13, handle substrate 104 col 3, lines 30-55);
removing the first substrate (Fig 13-15, removed sacrificial substrate 902); and
forming a third epitaxial semiconductor layer (device layer 108 are formed by epitaxy, col 10, lines 55-68) over the first epitaxial semiconductor layer (buffer layer 904, col 9, lines 10-55).
But Chou does not disclose explicitly wherein a resistivity of the third epitaxial semiconductor layer is different than a resistivity of the second epitaxial semiconductor layer.
In a similar field of endeavor, Yonchara discloses wherein a resistivity of the third epitaxial semiconductor layer is different than a resistivity of the second epitaxial semiconductor layer ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou in light of Yonchara teaching “wherein a resistivity of the third epitaxial semiconductor layer is different than a resistivity of the second epitaxial semiconductor layer ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45)” for further advantage such as produces semiconductor wafers having efficient and low defects.
Regarding claim 14. Chou and Yonchara discloses the method of claim 13, Chou further discloses wherein a thickness of the third epitaxial semiconductor layer (In some embodiments, a thickness T.sub.d of the device layer 108 is less than about 10, 50, 110, 120, or 150 nanometers) is less than a thickness of the first epitaxial semiconductor layer (a thickness T.sub.b of the buffer layer 904 is between about 1.8-4 micrometers, about 1-3 micrometers, or about 3-4 micrometers) and a thickness of the second epitaxial semiconductor layer (a thickness T.sub.es of the etch stop layer 1002 is between about 10-200 nanometers, about 30-140 nanometers, about 10-100 nanometers, or about 100-200 nanometers).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Regarding claim 15. Chou and Yonchara discloses the method of claim 14, Chou further discloses wherein a total thickness of the first epitaxial semiconductor layer (a thickness T.sub.b of the buffer layer 904 is between about 1.8-4 micrometers, about 1-3 micrometers, or about 3-4 micrometers), the second epitaxial semiconductor layer (a thickness T.sub.es of the etch stop layer 1002 is between about 10-200 nanometers, about 30-140 nanometers, about 10-100 nanometers, or about 100-200 nanometers), and the third epitaxial semiconductor layer is between 4 µm and 12 µm (In some embodiments, a thickness T.sub.d of the device layer 108 is less than about 10, 50, 110, 120, or 150 nanometers).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Regarding claim 16. Chou and Yonchara discloses the method of claim 13, Yonchara discloses wherein the resistivity of the second epitaxial semiconductor layer is greater than the resistivity of the third epitaxial semiconductor layer by at least a factor of five ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45. Therefore, second resistivity of the second epitaxial semiconductor layer can greater than the first resistivity of the first epitaxial semiconductor layer by a factor of five).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou in light of Yonchara teaching “wherein the resistivity of the second epitaxial semiconductor layer is greater than the resistivity of the third epitaxial semiconductor layer by at least a factor of five ( “It will be good if density of impurity of the epitaxial layer 32 is higher than density of impurity of the epitaxial layer 31, and in particular a resistivity of the first epitaxial layer 31 falls within the range of 0.02 to 10000 .OMEGA.cm, more preferably 0.1 to 100 .OMEGA.cm, and a resistivity of the second epitaxial layer 32 falls within the range of 0.001 to 0.1 .OMEGA.cm, more preferably 0.005 to 0.02 .OMEGA.cm so that the resistivity of the epitaxial layer 32 is lower than the resistivity of the epitaxial layer 31”, col 27, lines 25-45. Therefore, second resistivity of the second epitaxial semiconductor layer can greater than the first resistivity of the first epitaxial semiconductor layer by a factor of five)” for further advantage such as produces semiconductor wafers having efficient and low defects.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US 10,395,974 A1; hereafter Chou) in view of Yonchara et al (US 6468,923 A1; hereafter Yonchara) as applied claims above and further in view of Wu et al (US 2020/0058746; hereafter Wu).
Regarding claim 8. Chou and Yonchara discloses the method of claim 1, Chou further discloses further comprising:
forming the second dielectric capping layer (Fig [8-21], insulating layer 106a, col 8, lines 50-68) over the second substrate (Fig 13, handle substrate 104, col 3, lines 30-55); and
performing a treatment (PVD, col 8, lines 55-68) of at least one of the first dielectric capping layer (Fig [8-21], insulating layer 106b, col 12, lines 1-35) and the second dielectric capping layer (Fig [8-21], insulating layer 106a, col 8, lines 50-68) prior to bonding the first dielectric capping layer (Fig [8-21], insulating layer 106b, col 12, lines 1-35) to the second dielectric capping layer (Fig [8-21], insulating layer 106a, col 8, lines 50-68).
But Chou and Yonchara does not disclose explicitly performing a plasma treatment.
In a similar field of endeavor, Wu discloses performing a plasma treatment (“cap dielectric layer 608 is deposited by plasma-enhanced PVD to achieve such localization, Para [ 0051]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou and Yonchara in light of Wu teaching “performing a plasma treatment (“cap dielectric layer 608 is deposited by plasma-enhanced PVD to achieve such localization, Para [ 0051])” for further advantage such as formation of insulating layer with well-known deposition techniques.
Regarding claim 9. Chou and Yonchara discloses the method of claim 1, But Chou and Yonchara does not disclose explicitly wherein bonding the first dielectric capping layer to the second dielectric capping layer comprises performing a dielectric-to-dielectric bond in a vacuum or reduced pressure environment.
In a similar field of endeavor, Wu discloses wherein bonding the first dielectric capping layer to the second dielectric capping layer comprises performing a dielectric-to-dielectric bond in a vacuum or reduced pressure environment (Para [ 0058]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou and Yonchara in light of Wu teaching “wherein bonding the first dielectric capping layer to the second dielectric capping layer comprises performing a dielectric-to-dielectric bond in a vacuum or reduced pressure environment (Para [ 0058])” for further advantage such as improve performance for the semiconductor devices.
Regarding claim 10. Chou and Yonchara discloses the method of claim 1, Chou further discloses “buffer layer 904 is or comprises monocrystalline silicon, the same material as the sacrificial substrate 902, some other semiconductor material, or any combination of the foregoing. In some embodiments, the buffer layer 904 is doped with n-type or p-type dopants and/or has a doping concentration less than about 10.sup.17, 10.sup.16, or 10.sup.15 cm.sup.−3. For example, the buffer layer 904 may be or comprise P− monocrystalline silicon”, and “etch stop layer 1002 is or comprises silicon germanium, silicon carbide, some other crystalline material, or any combination of the foregoing. In some embodiments where the etch stop layer 1002 is or comprises silicon germanium, a concentration of germanium in the etch stop layer 1002 is between about 20-60, 20-40, or 40-60 atomic percent relative to silicon in the etch stop layer 1002. For example, the etch stop layer 1002 may be or comprise, for example, Si.sub.xGe.sub.1-x”.
But Chou and Yonchara does not disclose explicitly wherein the first epitaxial semiconductor layer and the second epitaxial semiconductor layer comprise the same semiconductor material that is doped with dopants of a first conductivity-type, wherein a doping concentration of the first epitaxial semiconductor layer is different than the doping concentration of second epitaxial semiconductor layer.
In a similar field of endeavor, Wu discloses wherein the first epitaxial semiconductor layer and the second epitaxial semiconductor layer comprise the same semiconductor material that is doped with dopants of a first conductivity-type, wherein a doping concentration of the first epitaxial semiconductor layer is different than the doping concentration of second epitaxial semiconductor layer ( Para [ 0045] discloses “ buffer layer 604, are or comprise P− silicon” and “etch stop layer 606 is or comprises silicon germanium, silicon carbide, silicon, some other crystalline material, or any combination of the foregoing, and/or is doped with boron, aluminum, some other p-type dopant, or any combination of the foregoing. For example, the etch stop layer 606 may be or comprise intrinsic (i.e., undoped) silicon germanium, boron-doped silicon germanium, or boron-doped elemental silicon. For example, the etch stop layer 606 may be or comprise Si.sub.xGe.sub.1-x, where x is about 0.2-0.6, about 0.2-0.4, or about 0.4-0.6. In some embodiments in which the etch stop layer 606 is doped with boron, the doping concentration may be about 1×10.sup.19 to about 5×10.sup.21 atoms per cubic centimeter (cm.sup.3), about 1×10.sup.19 to about 5×10.sup.20 atoms/cm.sup.3, about 5×10.sup.20 to about 5×10.sup.21 atoms/cm.sup.3, or about 5×10.sup.19 to about 3×10.sup.21 atoms/cm.sup.3”. Based on that, first epitaxial semiconductor layer and the second epitaxial semiconductor layer can have the same semiconductor material that is doped with dopants of a first conductivity-type, wherein a doping concentration of the first epitaxial semiconductor layer can be different than the doping concentration of second epitaxial semiconductor layer).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou and Yonchara in light of Wu teaching to have epitaxial layer with different concentration for further advantage such as improve performance for the semiconductor devices.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US 10,395,974 A1; hereafter Chou) in view of Yonchara et al (US 6468,923 A1; hereafter Yonchara) as applied claims above and further in view of Jiken et al (US 2006/0226514; hereafter Jiken).
Regarding claim 12. Chou and Yonchara discloses the method of claim 11, Chou further discloses wherein the third epitaxial semiconductor layer (Fig [8-21], device layer 108 are formed by epitaxy) is comprised of the same material (monocrystalline silicon) as the first epitaxial semiconductor layer (Fig [8-21], buffer layer 904 is or comprises monocrystalline silicon).
But Chou and Yonchara does not disclose explicitly the third epitaxial semiconductor layer has a third resistivity that is within 10% of the first resistivity of the first epitaxial semiconductor layer or the second resistivity of the second epitaxial semiconductor layer.
In a similar field of endeavor, Jiken discloses the third epitaxial semiconductor layer has a third resistivity that is within 10% of the first resistivity of the first epitaxial semiconductor layer or the second resistivity of the second epitaxial semiconductor layer (Table 1 and Table 2).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou and Yonchara in light of Jiken teaching to have desire resistivity in the epitaxial layer w for further advantage such as improve performance for the semiconductor devices.
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US 10,395,974 A1; hereafter Chou) in view of Park et al (US 2009/0250753 A1; hereafter Park).
Regarding claim 21. Chou discloses a method of forming a semiconductor device (Fig [8-21]), comprising:
forming a second epitaxial semiconductor layer (Fig [8-21], etch stop layer 1002, col 10, lines 10-55) over a first epitaxial semiconductor layer (Fig [8-21], buffer layer 904, col 9, lines 10-55) that is located on a first substrate (Fig [8-21], sacrificial substrate 902 col 9, lines 10-55);
forming a first dielectric capping layer (Fig [8-21], insulating layer 106b) over the second epitaxial semiconductor layer (Fig [8-21], etch stop layer 1002);
bonding the first dielectric capping layer (Fig [8-21], insulating layer 106b, col 12, lines 1-35) to a second dielectric capping layer (Fig [8-21], insulating layer 106a, col 8, lines 50-68) located on a second substrate (Fig 13, handle substrate 104, col 3, lines 30-55);
removing the first substrate ( Fig 13-15, removed sacrificial substrate 902) to provide a semiconductor-on-insulator (SOI) structure comprising the first epitaxial semiconductor layer (buffer layer 904, col 9, lines 10-55) and the second epitaxial semiconductor layer (etch stop layer 1002 , col 10, lines 10-55) on the second substrate (Fig 13, handle substrate 104, col 3, lines 30-55), and a buried insulator layer ( insulating layers [106a, 106b]) comprising the first dielectric capping layer (Fig [8-21], insulating layer 106b, col 12, lines 1-35) and the second dielectric capping layer (Fig [8-21],insulating layer 106a, col 8, lines 50-68) located between the second epitaxial semiconductor layer (Fig [8-21],etch stop layer 1002 , col 10, lines 10-55) and the second substrate (Fig 13, handle substrate 104, col 3, lines 30-55).
But Chou does not disclose explicitly forming at least one high-voltage device having an operating voltage greater than 50 volts and at least one low-voltage device having an operating voltage less than 50 volts on the SOI structure.
In a similar field of endeavor, Park discloses forming at least one high-voltage device having an operating voltage greater than 50 volts and at least one low-voltage device having an operating voltage less than 50 volts on the SOI structure (Fig 6, Para [ 0052] discloses “ a silicon on insulator (SOI) substrate 200 includes a first active region 202, on which the bipolar transistor will be formed, a second active region 205, on which the CMOS transistor will be formed, and a third active region 208, on which the DMOS transistor will be formed, is provided”, which are high voltage, and low voltage transistors).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou in light of Park teaching “forming at least one high-voltage device having an operating voltage greater than 50 volts and at least one low-voltage device having an operating voltage less than 50 volts on the SOI structure (Fig 6, Para [ 0052] discloses “ a silicon on insulator (SOI) substrate 200 includes a first active region 202, on which the bipolar transistor will be formed, a second active region 205, on which the CMOS transistor will be formed, and a third active region 208, on which the DMOS transistor will be formed, is provided”, which are high voltage, and low voltage transistors)” for further advantage such as high integration reliable semiconductor device formation.
Examiner like to note that wherein “at least one high-voltage device having an operating voltage greater than 50 volts and at least one low-voltage device having an operating voltage less than 50 volts”, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto , 136 USPQ 458, 459 (CCPA 1963). In this case the structure is capable of performing this use.
Regarding claim 22. Chou and Park disclose the method of claim 21, Park further disclose wherein the at least one high-voltage device comprises at least one double diffused metal oxide semiconductor (DMOS) device (Fig 6, Para [ 0052]) and the at least one low- voltage device comprises at least one bipolar device and at least one complementary metal oxide semiconductor (CMOS) device (Fig 6, Para [ 0052]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou in light of Park teaching “wherein the at least one high-voltage device comprises at least one double diffused metal oxide semiconductor (DMOS) device (Fig 6, Para [ 0052]) and the at least one low- voltage device comprises at least one bipolar device and at least one complementary metal oxide semiconductor (CMOS) device (Fig 6, Para [ 0052])”, which are high voltage, and low voltage transistors)” for further advantage such as high integration reliable semiconductor device formation.
Regarding claim 23. Chou and Park disclose the method of claim 1, Chou further discloses wherein the first epitaxial semiconductor layer has a thickness between 0.1 µm and 10 µm (a thickness T.sub.b of the buffer layer 904 is between about 1.8-4 micrometers, about 1-3 micrometers, or about 3-4 micrometers), and the second epitaxial semiconductor layer has a thickness between 0.1 µm and 10 µm (a thickness T.sub.es of the etch stop layer 1002 is between about 10-200 nanometers, about 30-140 nanometers, about 10-100 nanometers, or about 100-200 nanometers). In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). >See also In re Harris, 409 F.3d 1339, 74 USPQ2d 1951 (Fed. Cir. 2005).
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US 10,395,974 A1; hereafter Chou) in view of Yonchara et al (US 6468,923 A1; hereafter Yonchara) and Wu et al (US 2020/0058746; hereafter Wu) as applied claims above and further in view of Vervuurt et al (US 2020/0027746; hereafter Vervuurt).
Regarding claim 24. Chou and Yonchara in light of Wu discloses the method of claim 8, but the combination fails to disclose further comprising performing a precleaning process to remove particulates and contaminants from an outer surface of at least one of the first dielectric capping layer and the second dielectric capping layer prior to performing the plasma treatment.
In a similar field of endeavor, Park discloses a precleaning process to remove particulates and contaminants from an outer surface of at least one of the first dielectric capping layer and the second dielectric capping layer prior to performing the plasma treatment (Para [ 0002-0004]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Chou, Yonchara and Wu in light of Vervuurt teaching “a precleaning process to remove particulates and contaminants from an outer surface of at least one of the first dielectric capping layer and the second dielectric capping layer prior to performing the plasma treatment (Para [ 0002-0004])” for further advantage such as to provide smooth and uniform dielectric surface.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
Prosecution Insights