Prosecution Insights
Last updated: August 17, 2026
Application No. 18/425,264

THERMAL CONDUCTIVE BARRIER LAYER IN INTERCONNECT STRUCTURE

Non-Final OA §102§103
Filed
Jan 29, 2024
Priority
Oct 27, 2023 — provisional 63/593,618
Examiner
NGUYEN, CUONG B
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
855 granted / 970 resolved
+20.1% vs TC avg
Strong +16% interview lift
Without
With
+15.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
49 currently pending
Career history
1014
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
46.2%
+6.2% vs TC avg
§102
32.2%
-7.8% vs TC avg
§112
18.1%
-21.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 970 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment Applicant's amendment to the claims, filed on May 11th, 2026, is acknowledged. Entry of amendment is accepted and made of record. Election/Restrictions Applicant's election without traverse of Group I (Claims 1-16 and new added claims 21-24) in the reply filed on May 11th, 2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MRUNAL ABHIJITH et al. (Pub. No.: US 2021/0225762 A1), hereinafter as MRUNAL ABHIJITH. Regarding claim 21, MRUNAL ABHIJITH discloses a method of forming a semiconductor structure in Figs. 4-5, 7A-7O, comprising: forming first and second conductive features (left and right conductive regions EP) in a first dielectric layer (passivation layer 0) (see Fig. 4 and [0022-0023], [0040]); depositing a second dielectric layer (layer 9 and layer 10) over the first dielectric layer (see Fig. 5 and [0041]); etching the second dielectric layer to form first (left hole RA) and second openings (right hole RA) to expose top surfaces of the first and second conductive features, respectively (see Fig. 7A and [0041]); depositing a thermal conductive layer (layer 40) to line sidewalls of the first and second opening and cover a top surface of the second dielectric layer between the first and second openings (see Fig. 6A and [0026-0026); depositing third and fourth conductive features (each portion of conductive material 4M in each hole RA) in the first and second openings, respectively (see Fig. 7B and [0062]); depositing a third dielectric layer (layer 19 and layer 20) over the second dielectric layer, the third dielectric layer interfacing with a horizontal portion of the thermal conductive layer that extends continuously from the third conductive feature to the fourth conductive feature (see Fig. 7D and [0063]); and forming a thermal conductive via (conductive via 5VG) extending through the second and third dielectric layers and interfacing with the horizontal portion of the thermal conductive layer (see Fig. 7I and [0069-0070]). Regarding claim 23, MRUNAL ABHIJITH discloses the method of claim 21, wherein the thermal conductive layer is a two-dimensional (2D) material layer (dielectric layer 40 has at least 2D), and the thermal conductive via (ruthenium) and the thermal conductive layer (silicon oxide) include different thermal conductive materials (see [0026] and [0036]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: a. Determining the scope and contents of the prior art. b. Ascertaining the differences between the prior art and the claims at issue. c. Resolving the level of ordinary skill in the pertinent art. d. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over MRUNAL ABHIJITH et al. (Pub. No.: US 2021/0225762 A1), hereinafter as MRUNAL ABHIJITH as applied to claim 21 above, and further in view of Tsai et al. (Pub. No.: US 2014/0264709 A1), hereinafter as Tsai. Regarding claim 22, MRUNAL ABHIJITH discloses the method of claim 21, but fails to disclose wherein the thermal conductive layer is spaced apart from the top surfaces of the first and second conductive features, the method further comprising: depositing a liner filling gaps between the thermal conductive layer and the first and second conductive features. Tsai discloses a method comprising a thermal conductive layer (dielectric layer 602) is spaced apart from top surfaces of the first (plug 702) and second conductive features (plug 704), the method further comprising: depositing a liner (barrier layer 710) filling gaps between the thermal conductive layer and the first and second conductive features (see Fig. 9 and [0029], [0032-0034]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the liner of Tsai into the method of MRUNAL ABHIJITH for filling the gap between the thermal conductive layer and the first and second conductive features because the modified method would prevent metal diffusion and further protect the conductive plug from being corrosion. Allowable Subject Matter Claim 24 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having: further comprising: prior to the depositing of the thermal conductive layer, forming an inhibitor film covering the top surfaces of the first and second conductive features; and after the depositing of the thermal conductive layer, removing the inhibitor film to expose the top surfaces of the first and second conductive features as recited in claim 24. Claims 1-16 are allowed over prior art of record. The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following: Removing a portion of the conductive material to expose the second portion of the thermal conductive layer and forming a third dielectric layer on the second portion of the thermal conductive layer and on the second dielectric layer as recited in claim 1. Claims 2-10 depend on claim 1, and therefore also include said claimed limitation. Depositing a conductive material filling the opening and performing a planarization process to remove a top portion of the conductive material and the liner layer to expose the two-dimensional material layer, wherein the two-dimensional material layer remains covering the top surface of the dielectric layer as recited in claim 11. Claims 12-16 depend on claim 11, and therefore also include said claimed limitation. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CUONG B NGUYEN/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Jan 29, 2024
Application Filed
Jul 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+15.6%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 970 resolved cases by this examiner. Grant probability derived from career allowance rate.

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