Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18425333 filed on 01/29/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of claims 18-37 in the reply filed on 5/18/206 is acknowledged.
Allowable subject matter
Claims 29-30 are objected to as being dependent upon a rejected base claim (independent claim 26), but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Trinh et al. (US 2021/0066587).
With respect to dependent claims 29-30, the cited prior art does not anticipate or make obvious, inter alia, the step of: “wherein a bottom surface of the switching layer is vertically offset from a top surface of the oxygen affinity layer by a first vertical distance, wherein a bottom surface of the metal layer is laterally offset from a top surface of the top electrode layer by a second vertical distance, wherein a first ratio between the first vertical distance and the second vertical distance is within a range of 0.1 to 0.2”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 32 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 32 recites the limitation “second switching layer”. The metes and bounds of the claimed limitation can not be determined for the following reasons: This limitation has not been defined before and therefore it is unclear what element the limitation is referring to.
For the purpose of the examination, the term “second switching layer” as recited will be considered as the switching layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18-25 are rejected under 35 U.S.C. 103 as being unpatentable over Trinh et al. (US 2021/0066587) in view of Lin et al. (US 2021/0273161).
Regarding Independent claim 18, Trinh et al. teach a method for forming an integrated chip, the method comprising:
forming a lower conductive wire (Fig. 6, element 116, paragraph 0019) over a substrate (Figs. 1 & 6, element 102, paragraph 0019);
forming a stack of memory layers over the lower conductive wire, wherein the stack of memory layers comprises a dielectric layer (Fig. 6, element 128, paragraph 0020, paragraph 0024-0026), a first oxygen affinity layer (Fig. 6, element 130, paragraph 0024-0026) over the dielectric layer, a metal layer (Fig. 6, element 134, paragraph 0020) over the first oxygen affinity layer, and a top electrode (Fig. 6, element 508, paragraph 0038) over the metal layer,
wherein a first Gibbs free energy of the first oxygen affinity layer is less than a second Gibbs free energy of the dielectric layer, and wherein a first difference between the first Gibbs free energy and the second Gibbs free energy is less than -100 kJ/mol (paragraph 0024-0026 disclose the same material as the instant application for the first oxygen affinity layer and the dielectric layer, accordingly the properties/intended use would be the same);
forming a masking layer (Fig. 11, element 1102, paragraph 0054) over the stack of memory layers; and
patterning (Fig. 12, paragraph 0055) the stack of memory layers according to the masking layer, thereby defining a memory cell.
Trinh et al. do not explicitly disclose a diffusion barrier layer over the first oxygen affinity layer and a metal layer over the diffusion barrier layer.
Lin et al. teach a memory device comprising a diffusion barrier layer (Fig. 2, element 116, paragraph 0030) over the first oxygen affinity layer (Fig. 2, element 114, paragraph 0027 discloses the same material as the instant application) and a metal layer (Fig. 2, element 118, paragraph 0040) over the diffusion barrier layer, and a top electrode (Fig. 2, element 120, paragraph 0041) over the metal layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Trinh et al. according to the teachings of Lin et al. with the motivation to “to prevent or slow material from diffusing from and/or into the data storage layer 114”.
Regarding claim 19, Trinh et al. modified by Lin et al. teach wherein the stack of memory layers further comprises a second oxygen affinity layer (Fig. 6, element 132, paragraph 0024-0026 of Trinh) disposed between the first oxygen affinity layer and the diffusion barrier layer, wherein a third Gibbs free energy of the second oxygen affinity layer is less than the first Gibbs free energy (paragraph 0024-0026 of Trinh disclose the same material as the instant application for the first and second oxygen affinity layer, accordingly the properties/intended use are the same).
Regarding claim 20, Trinh et al. modified by Lin et al. teach wherein intrinsic oxygen vacancies are formed within the dielectric layer before forming the masking layer over the stack of memory layers (paragraph 0022, 0028 of Trinh).
Regarding claim 21, Trinh et al. modified by Lin et al. teach wherein a thickness of the dielectric layer is greater than or equal to a thickness of the first oxygen affinity layer, wherein a thickness of the metal layer is greater than the thickness of the dielectric layer (paragraph 0024 of Trinh and paragraph 0034-0035, 0039 of Lin discloses a range of thickness for different layers. Accordingly, the thickness is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention).
Regarding claim 22, Trinh et al. modified by Lin et al. teach wherein the metal layer comprises a metal (paragraph 0020, 0036 of Trinh) and the diffusion barrier layer comprises a metal nitride of the metal (paragraph 0031 of Lin), wherein a thickness of the diffusion barrier layer is greater than the thickness of the dielectric layer (paragraph 0024 of Trinh and paragraph 0034-0035, 0039 of Lin discloses a range of thickness for different layers. Accordingly, the thickness is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention).
Regarding claim 23, Trinh et al. modified by Lin et al. teach forming a sidewall spacer (Fig. 6, element 510, paragraph 0037 of Trinh) structure around the memory cell, wherein the sidewall spacer structure comprises a bottom surface aligned with a lower lateral surface of the dielectric layer (Fig. 6 of Trinh), wherein the dielectric layer comprises a lower curved surface below the lower lateral surface (Fig. 6 of Tring).
Regarding claim 24, Trinh et al. modified by Lin et al. teach wherein outer sidewalls of the dielectric layer are aligned with outer sidewalls of the first oxygen affinity layer (Fig. 6 of Trinh), wherein outer sidewalls of the metal layer are spaced between the outer sidewalls of the first oxygen affinity layer (Fig. 6 of Trinh).
Regarding claim 25, Trinh et al. modified by Lin et al. teach wherein the first Gibbs free energy is less than -1,000 kJ/mol (paragraph 0024-0026 disclose the same material as the instant application for the first oxygen affinity layer, accordingly the properties/intended use would be the same).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 26-28, 31-34, 36-37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Trinh et al. (US 2021/0066587).
Regarding Independent claim 26, Trinh et al. teach a method for forming an integrated chip, the method comprising:
forming a first conductive interconnect (Fig. 10, element 116, paragraph 0019) in a first dielectric layer (Fig. 10, element 501, paragraph 0036) over a substrate (Figs. 1 & 10, element 102, paragraph 0019);
deposit a second dielectric layer (Fig. 10, element 502, paragraph 0036) over the first conductive interconnect;
patterning the second dielectric layer to from an opening in the second dielectric layer that exposes an upper surface of the first conductive interconnect (Fig. 10, paragraph 0053);
forming a stack of memory layers over the second dielectric layer and in the opening, wherein the stack of memory layers comprises a bottom electrode layer (Fig. 10, element 1006, paragraph 0053), a switching layer (Fig. 10, element 1008, paragraph 0020, paragraph 0024-0026, 0053) over the bottom electrode layer, an oxygen affinity layer (Fig. 10, element 1010, paragraph 0024-0026, 0053) over the switching layer, a metal layer (Fig. 10, element 1014, paragraph 0053) over the oxygen affinity layer, and a top electrode layer (Fig. 10, element 1016, paragraph 0038, 0053) over the metal layer,
wherein the oxygen affinity layer comprises a first metal oxide and the switching layer comprises a second metal oxide different from the first metal oxide (paragraph 0024-0026),
wherein the switching layer comprises a plurality of intrinsic oxygen vacancies (paragraph 0015-0016);
patterning the stack of memory layers to from a memory cell (Figs. 11-12, element 1004, paragraph 0054-0055);
depositing a third dielectric layer (Fig. 15, element 504, paragraph 0037) over the memory cell; and
forming a second conductive interconnect (Fig. 15, element 512, paragraph 0039) in the third dielectric layer and contacting the top electrode layer.
Regarding claim 27, Trinh et al. teach wherein the switching layer comprises a first segment over the first conductive interconnect and a second segment laterally offset from the first conductive interconnect, wherein a bottom surface of the first segment extends below a top surface of the bottom electrode layer, and wherein a bottom surface of the second segment directly contacts the top surface of the bottom electrode layer (Fig. 6).
Regarding claim 28, Trinh et al. teach wherein after patterning the stack of memory layers the bottom electrode layer has an outer sidewall facing a first direction, wherein an outer sidewall of the switching layer facing the first direction is laterally offset from the outer sidewall of the bottom electrode layer by a lateral distance greater than a thickness of the switching layer (Figs. 15-16 & 6).
Regarding claim 31, Trinh et al. teach wherein a conductive path is selectively formable in the switching layer and the oxygen affinity layer, wherein a width of the conductive path is greater in the oxygen affinity layer than in the switching layer (paragraph 0022).
Regarding claim 32, Trinh et al. teach wherein the bottom electrode layer contacts a curved sidewall (Fig. 6) of the second switching layer over the first conductive interconnect.
Regarding claim 33, Trinh et al. teach forming a sidewall spacer structure (Fig. 6, element 510, paragraph 0037) around the memory cell, wherein the sidewall spacer structure contacts a top surface of the bottom electrode layer (Fig. 6, element 124) and has outer sidewalls aligned with outer sidewalls of the bottom electrode layer.
Regarding Independent claim 34, Trinh et al. teach a method for forming an integrated chip, the method comprising:
forming a first conductive interconnect (Fig. 6, element 116, paragraph 0019) in a first dielectric layer (Fig. 6, element 502, paragraph 0036) over a substrate (Figs. 1 & 6, element 102, paragraph 0019);
forming a memory cell over the first conductive interconnect, wherein the memory cell comprises a first conductive structure over the first conductive interconnect (Fig. 6, element 120, paragraph 0019), a switching structure (Fig. 6, elements 128 & 130, paragraph 0020, 0024-0026), over the first conductive structure, and a second conductive structure (Fig. 6, element 134, paragraph 0020) over the switching structure,
wherein the switching structure comprises a switching layer (Fig. 6, element 128, paragraph 0020, paragraph 0024-0026), a first oxygen affinity layer (Fig. 6, element 130, paragraph 0024-0026), and a second oxygen affinity layer (Fig. 6, element 132, paragraph 0024-0026), wherein the first oxygen affinity layer is between the switching layer and the second oxygen affinity layer,
wherein a first difference between Gibbs free energies of the first oxygen affinity layer and the switching layer is greater than a second difference between Gibbs free energies of the second oxygen affinity layer and the first oxygen affinity layer (paragraph 0024-0026 disclose the same material as the instant application for the first oxygen affinity layer, the switching layer, and the second oxygen affinity layer, accordingly the properties/intended use would be the same);
depositing a second dielectric layer (Fig. 6, element 504, paragraph 0037) over the memory cell; and
forming a second conductive interconnect (Fig. 6, element 512, paragraph 0039) in the second dielectric layer and on the second conductive structure.
Regarding Independent claim 36, Trinh et al. teach wherein the first difference is within a range of about -100 to -250 kJ/mol and the second difference is within a range of about - 500 to -800 kJ/mol (paragraph 0024-0026 disclose the same material as the instant application for the first oxygen affinity layer, the switching layer, and the second oxygen affinity layer, accordingly the properties/intended use would be the same).
Regarding Independent claim 37, Trinh et al. teach wherein the switching layer comprises a first metal oxide, the first oxygen affinity layer comprises a second metal oxide, and the second oxygen affinity layer comprises a third metal oxide, wherein the switching layer, the first oxygen affinity layer, and the second oxygen affinity layer are each undoped (paragraph 0024-0026).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 35 is ejected under 35 U.S.C. 103 as being unpatentable over Trinh et al. (US 2021/0066587).
Regarding claim 35, Trinh et al. teach wherein thicknesses of the first oxygen affinity layer and the second oxygen affinity layer are less than a thickness of the switching layer (paragraph 0024 of Trinh discloses a range of thickness for different layers. Accordingly, the thickness is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed area is for a particular purpose that is critical to the overall claimed invention).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
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