DETAILED ACTION
This action is responsive to the application No. 18/425,352 filed on January 29, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I and Species A, shown in Fig. 2, corresponding to claims 1-8 and 21-32, in the reply filed on May 18, 2026, is acknowledged. Claims 1-8, requiring a top gate fabrication sequence, are drawn to a non-elected species, and are withdrawn from consideration. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for some of the stable, commercially available metals in groups 3-12 and periods 5-7, and elements of the lanthanide and actinide series, does not reasonably provide enablement for the use of all of the elements claimed. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make or use the invention commensurate in scope with these claims.
Claims 21-32 are ejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The range of elements includes many elements that are synthetic, have no stable isotopes, are only produced by the atom in particle accelerators and fission reactions, and have millisecond-to-hour half-lives, and thus useful amounts of material cannot be made or stored, which is a prerequisite for using these to manufacture a semiconductor device. The specification does not describe any method of synthesizing, handling, or integrating such short-lived, highly radioactive elements into semiconductor devices, nor does it provide any guidance that would enable a person of ordinary skill in the art of semiconductor processing to obtain and use these materials as electrodes without undue experimentation. Applicant has not demonstrated possession of the invention with respect to all of the elements claimed. In view of their nuclear properties and production limitations, fabricating a functional transistor comprising any of these elements would require not only the invention of new nuclear synthesis and materials-handling techniques but also the ability to maintain atom-scale quantities in a solid form long enough to complete device fabrication and testing, which is well beyond the current state of the art and not disclosed in the specification. Absent detailed guidance, a skilled artisan would have to engage in extensive, multi-disciplinary experimentation, far beyond routine semiconductor processing, to attempt to use all of these elements as a protective layer on transistor electrodes, which constitutes undue experimentation under the Wands factors. While the specification may enable the use of certain stable, commercially available metals such as ruthenium, rhodium, palladium, and iridium as protective layers on transistor electrodes, it does not enable the full scope of the claimed protection layer including any element from the recited list. With respect to Wands: the quantity of experimentation would require inventing new nuclear synthesis and fabrication processes. No known processes would be fast enough to use unstable materials with such short half-lives. There is no guidance in the specification for making a device using the synthetic, highly radioactive elements. Working examples are limited to ordinary stable metals. Integrating unstable, exotic nuclear materials into CMOS fabs is far outside of routine skill. There are no known prior art electrodes made of Np, Pu, Bk, Cf, Rg, etc.
Also, for long-lived radioactive elements (e.g. Th, U, Np, Pu, Am, etc.) used as an electrode material, the emitted radiation would interfere with transistor operation, both directly and indirectly. Transistors are sensitive to ionizing radiation and particle flux. Radiation from the material will generate charge in gate dielectric and the channel, producing trapped charge and interface states, excess noise, drift in operating point, and unpredictable behavior over the device lifetime. Even if one could physically obtain such an electrode, the specification doesn’t address or enable mitigation of these radiation-induced failure mechanisms.
In addition to the numerous issues discussed above, it is further noted mercury is included in the claimed elements. Mercury is a liquid at room temperature and also evaporates at room temperature and above. There is no disclosure of any process for coating the gate and contacts in a uniform protective layer (e.g. as shown in Fig. 2) of liquid mercury, or how to embed these Hg-coated electrodes in the surrounding and subsequent layers that are understood to be processed at elevated temperatures.
Also see Trustees of Boston Univ. v. Everlight Electronics Co., 896 F.3d 1357 (Fed. Cir., 2018).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 25 recites at least one of the two contact structures is formed to penetrate the channel. In view of the transistor of Fig. 2, the two contact structures correspond to the source/drain electrodes of the transistor. The channel of a transistor is defined by the region adjacent the gate and between the source and drain, the claimed contacts cannot penetrate the channel because the contacts define the ends or border of the channel. It is unclear what Applicant regards as the channel of the transistor and where the contacts penetrate the channel.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-24, 27-28, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ning et al. (US 2017/0040342).
(Re Claim 21) Ning teaches a method for manufacturing a semiconductor structure, comprising:
forming a gate electrode (Fig. 3: 2);
forming a gate dielectric (6);
forming a channel (active layer between 6 and 3/4, not labeled, ¶¶71-75) on the gate dielectric in a vertical direction; and
forming two contact structures (3 and 4) on the channel, the two contact structures being spaced apart from each other in a first direction different from the vertical direction (Fig. 3), at least one of the gate electrode and the two contact structures including a main body (3/4), and a protection layer (5) that includes a transition metal (silver, ¶80) which is one of elements of groups 3 to 12 in periods 5 to 7, elements of lanthanide series, and elements of actinide series.
(Re Claim 22) wherein the channel includes a metal oxide (¶74).
(Re Claim 23) wherein the channel includes indium gallium zinc oxide, indium oxide, gallium oxide, zinc oxide, tin oxide, copper oxide, or combinations thereof (¶74).
(Re Claim 24) wherein the main body and the protection layer are made of different materials (¶80).
(Re Claim 27) wherein each of the two contact structures has an upper end distal from the channel, the upper ends of the two contact structures being at different height levels (Fig. 3, one may select an upper end at the left side of 3 and the left side of 4 having different heights).
(Re Claim 28) Ning teaches a method for manufacturing a semiconductor structure, comprising:
forming a gate electrode (Fig. 3: 2);
forming a gate dielectric (6);
forming a channel spaced apart from the gate electrode (active layer between 6 and 3/4, not labeled, ¶¶71-75); and
forming two contact structures (3/4) on the channel, the two contact structures being spaced apart from each other, and being spaced apart from the gate electrode (Fig. 3), at least one of the gate electrode and the two contact structures including a main body (3/4), and a protection layer (5) that includes a first transition metal (silver, ¶80) which is one of elements of groups 3 to 12 in periods 5 to 7, elements of lanthanide series, and elements of actinide series.
(Re Claim 30) wherein the main body is enclosed by the protection layer (Fig. 3).
Claims 21, 25-26, 28, and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2009/0050894).
(Re Claim 21) Park teaches a method for manufacturing a semiconductor structure, comprising:
forming a gate electrode (Fig. 3A: 320);
forming a gate dielectric (330);
forming a channel (340) on the gate dielectric in a vertical direction; and
forming two contact structures (321+340a) on the channel, the two contact structures being spaced apart from each other in a first direction different from the vertical direction (Fig. 3B), at least one of the gate electrode and the two contact structures including a main body (321a or 321b), and a protection layer (the other of 321b or 321a) that includes a transition metal (¶¶66-67) which is one of elements of groups 3 to 12 in periods 5 to 7, elements of lanthanide series, and elements of actinide series.
(Re Claim 25) wherein at least one of the two contact structures is formed to penetrate the channel (Fig. 3B).
(Re Claim 26) wherein at least one of the two contact structures is formed to penetrate the gate dielectric, and is spaced apart from the gate electrode (Fig. 3B).
(Re Claim 28) Park teaches a method for manufacturing a semiconductor structure, comprising:
forming a gate electrode (Fig. 3A: 320);
forming a gate dielectric (330);
forming a channel (340) spaced apart from the gate electrode; and
forming two contact structures (321+340a) on the channel, the two contact structures being spaced apart from each other, and being spaced apart from the gate electrode (Fig. 3B), at least one of the gate electrode and the two contact structures including a main body (321a or 321b), and a protection layer (the other of 321b or 321a) that includes a transition metal (¶¶66-67) which is one of elements of groups 3 to 12 in periods 5 to 7, elements of lanthanide series, and elements of actinide series.
(Re Claim 29) wherein each of the two contact structures includes the main body and the protection layer, the main body being spaced apart from the channel by the protection layer (Fig. 3B, from claim 28 selecting the main body to be 321a).
Claims 28 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tan et al. (US 2023/0369503).
(Re Claim 28) Tan teaches a method for manufacturing a semiconductor structure, comprising:
forming a gate electrode (Fig. 2A: 210);
forming a gate dielectric (212);
forming a channel (214) spaced apart from the gate electrode; and
forming two contact structures (Fig. 2K:250/252) on the channel, the two contact structures being spaced apart from each other, and being spaced apart from the gate electrode (Fig. 2K), at least one of the gate electrode and the two contact structures including a main body, and a protection layer that includes a transition metal (¶43 main fill (body)+work function (protection), Pt, Pd, Au, etc.) which is one of elements of groups 3 to 12 in periods 5 to 7, elements of lanthanide series, and elements of actinide series.
(Re Claim 31) further comprising: forming a first electrode of a capacitor, the first electrode being connected to one of the two contact structures; forming a second electrode of the capacitor; and forming a dielectric interposed between the first electrode and the second electrode (Fig. 2M, 260: 264, 268, 266).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related transistors, protective layers, and capacitors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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