DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
The passivation coatings are identified as “216” and “416” in the specification. These elements are identified as “219” and “419” in Figs. 2 and 4.
The channel stoppers are identified as “414” in the specification. This element is identified as “413” in the drawings.
Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4)-(5) because:
Reference character “214” has been used to designate both the moat and the anode in Fig. 2.
Reference character “414” has been used to designate the anode in Fig. 4, but is duplicated elsewhere in the figure.
Reference characters “219”, “419”, “413” are not mentioned in the description.
Reference character “216” has been used to designate the passivation coating in Fig. 3, but that element is designed as “219” in Fig. 4.
Reference character “416” has been used to designate the passivation coating in Fig. 5, but that element is designed as “419” in Fig. 4.
The drawings are objected to because of the following informalities:
The moat and passivation layer in Fig. 2 are illustrated as if a layer is formed which fills the moat over the passivation layer, however no corresponding layer is disclosed or identified.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding independent claims 1, 17, and 19, the limitation “the [lower] base layer including an anode” renders the claims indefinite, as the lower base layer is a doped region formed in the substrate (see Spec at [0019]) and the anode is a terminal connected to the base layer (see Spec at [0026] and [0028]). Therefore it is unclear structurally how the base layer can “include” the anode. In light of the Specification, for purposes of examination the claim will be interpreted as “the [lower] base layer connected to an anode”.
Claims 2-16, 18, and 20 depend from independent claims 1, 17, and 19 and are therefore correspondingly indefinite.
Regarding claim 5, the limitation “the upper base layer including a gate” and “the top layer including a cathode” render the claim indefinite for reasons analogous to the rejection of claim 1. The upper base layer and top layer are doped regions formed in the substrate and the gate and cathode are electrical terminals connected to the upper base layer and top layer, respectively (see Spec at [0019], [0026], [0028]). In light of the Specification, for purposes of examination the claim will be interpreted as “the upper base layer connected to a gate” and “the top layer connected to a cathode”.
Regarding claim 6, the limitation “the upper layer” renders the claim indefinite, as there is no antecedent basis for this limitation. For purposes of examination the limitation will be interpreted as “upper base layer”.
Regarding claim 12, the limitation “forming a respective channel stopper in each of a plurality of exposed regions of the upper base layer” renders the claim indefinite, as it contradicts the specification. See MPEP 2173.03. The specification and figures only depict the channel stopper formed in the substrate, outside of the upper base layer (Fig. 4, [0033]). For purposes of examination, the limitation will be interpreted as “forming a respective channel stopper in each of a plurality of exposed regions of the upper surface of the substrate”.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 2 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Independent claim 1 requires that the tub structure is disposed such that “presence of the tub structure reduces a thickness of the drift region”. Dependent claim 2 requires that “the thickness is reduced relative to a corresponding thickness of the drift region absent the tub structure”. Reducing a thickness of the drift region is a relative description that already requires comparison to the drift region without the tub structure.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (JP 2019-169563 A) in view of Zhang (CN 110690280 B).
Regarding claims 1-2, Takahashi teaches a method of fabricating a semiconductor device in a wafer (Figs. 5A-5D, [0027], thyristor), the method comprising:
providing a substrate layer (Fig. 5A(1), 10, [0058]),
providing an isolation structure that laterally isolates the semiconductor device from other semiconductor devices in the wafer (Fig. 5A(4), 13, [0059]), and
providing a base layer disposed under the substrate layer, the base layer connected to an anode having an associated active region that includes a drift region in the substrate layer (Fig. 5B(3), 15, [0063]-[0067]; [0029]).
Takahashi does not explicitly teach forming a tub structure in the substrate layer, wherein the tub structure is disposed inside the active region such that presence of the tub structure reduces a thickness of the drift region.
Zhang teaches a method of fabricating a thyristor comprising providing a base layer connected to an anode having an associated active region that includes a drift region in the substrate layer (Fig. 1, 10, 221, 52, [0047]), and forming a tub structure inside the active region such that the presence of the tub structure reduces a thickness of the drift region ([0047]-[0048]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Zhang with Takahashi such that the method comprises a tub structure in the substrate layer, wherein the tub structure is disposed inside the active region such that presence of the tub structure reduces a thickness of the drift region, for the purpose of controlling the breakdown voltage of the device (Zhang, [0046], [0051]).
Regarding claim 3, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01. Therefore the combination of Takahashi and Zhang, which teaches the tub structure as claimed, teaches wherein the tub structure is formed to reduce a peak on-state voltage (VTM) of the semiconductor device, wherein the peak on-state voltage is reduced without impairing a capability of voltage blocking in the isolation structure when the semiconductor device is in a state of reverse bias. It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 4 , the combination of Takahashi and Zhang teaches wherein the semiconductor device comprises a thyristor, and wherein the substrate layer comprises silicon (Takashi, [0027], [0031]; Zhang, [0004]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 5, the combination of Takahashi and Zhang teaches wherein the base layer comprises a lower base layer (Takahashi, Fig. 2), and wherein the method further comprises:
providing (i) an upper base layer disposed over the substrate layer (14, [0035]) and (ii) a top layer disposed over the upper base layer (18, [0039]),
the upper base layer connected to a gate, the top layer connected to a cathode ([0085]).
It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 6, the combination of Takahashi and Zhang teaches wherein the top layer is smaller in area than the upper base layer, whereby the upper base layer is partially exposed, and wherein the substrate layer has a greater thickness than each of the lower base layer, the upper base layer, and the top layer (Takahashi, Fig. 1).
Regarding claim 7, the combination of Takahashi and Zhang teaches wherein the lower base layer, the substrate layer, the upper base layer, the top layer, and the isolation structure are of the wafer and are provided by:
forming the isolation structure by doping a first part of the substrate layer (Takahashi, Fig. 5A(4), [0061])
wherein the tub structure is formed by doping a second part of the substrate layer (Zhang, Fig. 8, [0069]-[0070]),
forming the lower base layer by doping a third part of the substrate layer (Takahashi, Fig. 5B(3), [0065]; Zhang, Fig. 9)
forming the upper base layer by doping a fourth part of the substrate layer (Takahashi, Fig. 5B(3), [0066]) and
forming the top layer by doping only a part of the upper base layer (Takahashi, Fig. 5D(3), Takahashi, [0084]).
It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 8, the combination of Takahashi and Zhang teaches wherein the lower base layer, the isolation structure, and the upper base layer are of a first polarity type (Takahashi, [0036], lower base layer 15 is p-type; [0034], isolation region 13 is p-type; [0035], upper base layer 14 is p-type) , and wherein the substrate layer and the top layer are of a second polarity type (Takahashi, [0031], substrate 20 is n-type; [0041], top-layer 18 is n-type). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 9, the combination of Takahashi and Zhang teaches wherein the first polarity type comprises a positive type (P type), and wherein the second polarity type comprises a negative type (N type) (see rejection of claim 8). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 10, the combination of Takahashi and Zhang teaches wherein the first polarity type comprises a negative type (N type), and wherein the second polarity type comprises a positive type (P type) (see rejection of claim 8; Takahashi, [0025], P/N types may be reversed). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 11, the combination of Takahashi and Zhang teaches wherein:
the lower base layer comprises a P lower base layer, the isolation structure comprises a P isolation structure, the substrate layer comprises an N− substrate layer, the upper base layer comprises a P upper base layer, and the top layer comprises an N+ top layer (Tahashi, [0036], lower base layer is p-type 10^17-10^19; [0034], isolation structure is p-type 10^18-10^20; [0031], substrate layer is n-type 10^13-10^16; [0035], upper base layer is p-type 10^17-10^19; [0041], top layer is n-type 10^19-10^20), or
the lower base layer comprises an N lower base layer, the isolation structure comprises an N isolation structure, the substrate layer comprises a P− substrate layer, the upper base layer comprises a P upper base layer, and the top layer comprises a P+ top layer (Takahashi, [0025], same as previous but with P/N types reversed). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 12, the combination of Takahashi and Zhang teaches wherein the upper base layer of the semiconductor device is smaller in area than the substrate layer of the semiconductor device, whereby the upper base layer of the semiconductor device is partially exposed prior to coating (Takahashi, Fig. 5D(2)), and wherein the method further comprises:
forming a respective channel stopper in each of a plurality of exposed regions of the upper surface of the substrate, wherein the respective channel stopper reduces a measure of current leakage by serving as a depletion region in the substrate layer (Takahashi, 19, Fig. 5D); and
forming, for each of one or more coating regions of the semiconductor device, a passivation of a respective coating atop the respective coating region, wherein the respective coating is selected from a glass coating and a film coating (Takahashi, Fig. 2, 6, [0046]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 13, the combination of Takahashi and Zhang teaches one or more coating regions comprising: a primary region disposed above at least the isolation structure; and one or more surface regions of the upper base layer of the semiconductor device (Takahashi, Fig. 2, 6, [0046]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 16, the combination of Takahashi and Zhang teaches dicing the semiconductor device to separate the semiconductor device from the wafer (Takahashi, [0062]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 1.
Regarding claim 17, Takahashi teaches a wafer for fabricating semiconductor devices (Fig. 2, [0027], thyristor), the wafer comprising:
an isolation structure that laterally isolates the semiconductor devices from one another in the wafer ([0034], 13); and
for each of the semiconductor devices:
a substrate layer (20, [0029]);
a lower base layer disposed below the substrate layer and the tub structure, the lower base layer connected to an anode having an associated active region that includes a drift region in the substrate layer (15, [0029]),
an upper base layer disposed above the substrate layer (14, [0029]), and
a top layer disposed above the upper base layer (18, [0029]).
Takahashi does not explicitly teach a tub structure formed in the substrate layer, wherein the tub structure is disposed inside the active region such that presence of the tub structure reduces a thickness of the drift region.
Zhang teaches a thyristor comprising providing a base layer connected to an anode having an associated active region that includes a drift region in the substrate layer (Fig. 1, 10, 221, 52, [0047]), and forming a tub structure inside the active region such that the presence of the tub structure reduces a thickness of the drift region ([0047]-[0048]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Zhang with Takahashi such that the device comprises a tub structure in the substrate layer, wherein the tub structure is disposed inside the active region such that presence of the tub structure reduces a thickness of the drift region, for the purpose of controlling the breakdown voltage of the device (Zhang, [0046], [0051]).
Regarding claim 18, the combination of Takahashi and Zhang teaches wherein the top layer is smaller in area than the upper base layer, and wherein the substrate layer is greater in thickness than each of the lower base layer, the upper base layer, and the top layer (Takahashi, Fig. 2). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi and Zhang for the reasons set forth in the rejection of claim 17.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (JP 2019-169563 A) in view of Zhang (CN 110690280 B) and Zhou (CN 113013241 A).
Regarding claim 14, the combination of Takahashi and Zhang does not explicitly teach forming a moat around the upper base layer of the semiconductor device to be fabricated, wherein the upper base layer comprises an island region circumscribed by the moat; and forming, for each of one or more coating regions of the semiconductor device, a passivation of a respective coating atop the respective coating region, wherein the respective coating is selected from a glass coating and a film coating.
Zhou teaches a thyristor comprising a wafer having a substrate layer and upper and lower base layers (Fig. 3, 10, 14, 12, [0055]), wherein the device may have a planar structure having an isolation structure that laterally isolates the device from other devices in the wafer and a passivation layer over the top surface of the substrate (Fig. 7, [0061]-[0062]), which is analogous to the structure in Takahashi, and further teaches as an alternative wherein the device has a moat around the upper base layer, the upper base layer comprises an island region circumscribed by the moat; and forming, for each of one or more coating regions of the semiconductor device, a passivation of a respective coating atop the respective coating region, wherein the respective coating is selected from a glass coating and a film coating (Fig. 5, 22, [0062]).
Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Zhou with Takahashi and Zhang such that the device has a moat around the upper base layer, the upper base layer comprises an island region circumscribed by the moat; and forming, for each of one or more coating regions of the semiconductor device, a passivation of a respective coating atop the respective coating region, wherein the respective coating is selected from a glass coating and a film coating because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A.
Regarding claim 15, the combination of Takahashi, Zhang, and Zhou teaches the one or more coating regions comprising the moat and one or more surface regions of the upper base layer of the semiconductor device (Zhou, Fig. 5), wherein prior to the coating being formed, the substrate layer of the semiconductor device is only exposed via the moat (Zhou, Fig. 3). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Takahashi, Zhang, and Zhou for the reasons set forth in the rejection of claim 14.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (CN 110690280 B).
Regarding claim 19, Zhang teaches a semiconductor device fabricated in a wafer (Fig. 13), the semiconductor device comprising:
a substrate layer (10, [0047]),
a tub structure formed in the substrate layer (222, [0047]),
a lower base layer disposed below the substrate layer and the tub structure, the lower base layer connected to anode having an associated active region that includes a drift region in the substrate layer, wherein the tub structure is disposed inside the active region such that presence of the tub structure reduces a thickness of the drift region (221, [0047]),
an upper base layer disposed above the substrate layer (211, [0048]); and
a top layer disposed above the upper base layer (31, [0049]).
Regarding claim 20, Zhang teaches wherein the top layer is smaller in area than the upper base layer, and wherein the substrate layer is greater in thickness than each of the lower base layer, the upper base layer, and the top layer.
Conclusion
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/ALIA SABUR/Primary Examiner, Art Unit 2812
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