Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 12
b. Pending: 1-3, 5-14 and 16-22
Claims 1, 3, 5, 12, 14 and 16 have been amended. Claims 4 and 15 have been canceled.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Specification
The new title is reviewed and accepted by examiner.
Previous abstract objection is withdrawn pursuant to amendments. However, amened line 5: “each of the stage calculating circuits….” causes ambiguity as there are no previous citation of term “stage calculating circuits”. Also, last line: “the second output bit being output as a correspond bit….” is unclear. Instead “corresponding bit” will be better choice.
Previous disclosure objection is withdrawn.
Appropriate corrections are required.
Claim Objections
Claim 3 and 14 objection are withdrawn pursuant to amendments.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Independent claims 1 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Line: 6-7 of claim 1 and
line: 5-6 of claim 12 both recite “each of the stage calculating circuits….” without prior mentioning of stage calculating circuits. Do they refer to same calculating circuits?
Line: 10-11 of claim 1 and line: 9 of claim 12 both recite “as a correspond bit of the output number signal”. Instead “corresponding bit” will be better choice.
All the dependent claims 2-3, 5-11, 13-14 and 16-22 carry the same deficit and henceforth rejected.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-22 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. US 20250252983 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the recite the same claim limitations in slightly varying languages. Even though independent claim 1 is amended by rolling in previous claim 4 (that is canceled); but Application No. US 20250252983, claim number 1, 4 and 5 together recites the same limitations and same reasonings hold true for the other independent claim 12.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 11-14, 16 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi et al. (US 20160078906) in view of Minotani et al. (WO 2022203059).
Regarding independent claim 1, Yamaguchi discloses a memory system (Figs. 1-5), comprising:
a plurality of memory dies stacked within the memory system (Fig. 1 and [0013] describes semiconductor chips Cp0 to CpM−1 stacked in sequence), each of the memory dies comprising:
a numbering circuit configured to generate an output number signal according to an input number signal (Fig. 1 and [0014]-[0015] describes transmission unit 3A), the numbering circuit comprising:
a plurality of calculating circuits coupled in series, each of the stage calculating circuits being configured to generate a first output bit and a second output bit, a current stage calculating circuit being configured to receive the first output bit from a previous stage calculating circuit and a corresponding bit of the input number signal to generate the first output bit and the second output bit as a correspond bit of the output number signal (Fig. 1 and [0014]-[0015] describes transmission unit 3A can be provided for each of the semiconductor chips Cp0 to CpM−1. The transmission unit 3A, based on chip identification information on a semiconductor chip in the present stage, can transmit chip identification information (or data for setting chip identification information) on a semiconductor chip in the next stage via the through electrodes V0 to VM−1. At that time, the direction in which the external signal S1 is sent between the semiconductor chips Cp0 to CpM−1 via the through electrodes V0 to VM−1 is set opposite to the direction in which chip identification information S2 is transmitted via the through electrodes V0 to VM−1. Specifically, the chip identification information S2 is transmitted from the semiconductor chip CpM−1 in the top layer to the semiconductor chip Cp0 in the bottom layer (or from the semiconductor chip Cp0 in the bottom layer to the semiconductor chip CpM−1 in the top layer). At that time, N (N is an integer of 2 or more) through electrodes V0 to VM−1 for use in transmission of the chip identification information S2 can be provided on each of the semiconductor chips Cp0 to CpM−1. The number N can be set to be equal to or more than the number of bits by which the M semiconductor chips Cp0 to CpM−1 can be identified. When 16 semiconductor chips Cp0 to Cp15 are stacked, the number N can be set to 4 or more. Fig. 4 and [0041]-[0047] shows two output lines from each stage and describes that semiconductor chip Cp15 is provided with four through electrodes V1 to V4 corresponding to the number of bits N=4),
wherein the calculating circuit comprises a first input end and a second input end, the first input end is coupled to receive the first output bit from the previous stage calculating circuit, and the second input end is coupled to receive the corresponding bit of the input number signal (Fig. 1 and [0014]-[0015] and Fig. 4 and [0041]-[0047]) and coupled to receive a first reference voltage through a preset resistor.
Yamaguchi does not explicitly teach receive a first reference voltage through a preset resistor, even though there are built-in resistances of wirings,
Minotani teaches receive a first reference voltage through a preset resistor (Fig. 7 and page: 8 describes that a resistor (Rb) connected to a voltage source is connected to the input of the difference average midpoint voltage calculation unit 403).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Minotani to Yamaguchi in order to provide with accurate amplification circuit as taught by Minotani (Abstract).
Regarding claim 2, Yamaguchi and Minotani together disclose all the elements of claim 1 as above and through Yamaguchi further the numbering circuit is configured to add a value of the input number signal with a predetermined difference to generate the output number signal (Figs. 1-4 and [0046]-[0047] describes one numbering circuit generating output signal based on previous circuit).
Regarding claim 3, Yamaguchi and Minotani together disclose all the elements of claim 2 as above and through Yamaguchi further the predetermined difference is one (Figs. 1-4 and [0046]-[0047] describes one numbering circuit getting input from the previous circuit. So, the predetermined difference is one).
Regarding claim 5, Yamaguchi and Minotani together disclose all the elements of claim 4 as above and through Yamaguchi further a plurality of bits of a predetermined number signal are respectively provided to the plurality of second input ends of the plurality of calculating circuits (Fig. 1 and [0025]).
Regarding claim 11, Yamaguchi and Minotani together disclose all the elements of claim 1 as above and through Yamaguchi further each calculating circuit comprises: an exclusive OR (XOR) gate configured to receive the first output bit from the previous stage calculating circuit and the corresponding bit of the input number signal to generate the second output bit as the corresponding bit of the output number signal; and an AND gate configured to receive the first output bit from the previous stage calculating circuit and the corresponding bit of the input number signal to generate the first output bit (Fig. 4 and corresponding sections of the specification show the prescribed connectivity).
Claims 12-14, 16 and 22 recite the exact claim limitations of claims 1-3, 5 and 11 respectively and henceforth rejected the same way.
Claims 10 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi et al. (US 20160078906) in view of Minotani et al. (WO 2022203059) and Tinker (US 20190332355).
Regarding claim10, Yamaguchi and Minotani together disclose all the elements of claim 1 as above and through Tinker further each calculating circuit is a half adder ([0013] describes half-adder being commonly used in calculating circuits).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Tinker to modified Yamaguchi in order to perform addition using half-adder as taught by Tinker ([0007]).
Claim 21 recite the exact claim limitations of claim 10 and henceforth rejected the same way.
Response to Arguments
Applicant's arguments/amendments filed on 1/5/2026 have been fully considered but they are not persuasive.
Last amended paragraph of independent claim 1 simply repeats same information as from second to last paragraph with the exception of preset resistor.
Previously used reference Yamaguchi in Fig. 4 and paragraph [0041]-[0047] discloses that semiconductor chip Cp15 is provided with four through electrodes V1 to V4 corresponding to the number of bits N=4.
New reference Minotani et al. (WO 2022203059) in Fig. 7 and
page: 8 describes that a resistor (Rb) connected to a voltage source is connected to the input of the difference average midpoint voltage calculation unit 403.
Rejections are maintained for above reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SULTANA BEGUM whose telephone number is (571)431-0691. The examiner can normally be reached M-F 8 am - 5 pm.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 2/12/2026