DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 11 – 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention (method) and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/01/2025.
Applicant’s election without traverse of claims 11 – 20 in the reply filed on 12/01/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hodono (JP2008-4855A; English Translation provided with Office Action).
Regarding Claim 1, Hodono (JP2008-4855A; English Translation provided with Office Action) discloses a semiconductor package film (Drawing 1,6a) comprising: a base film (BIL,30) having sprocket holes (1S) arranged in a first direction up-down direction in Fig 1 or 6a) in an edge area (area about the left or right edges as seen in Fig 1; note that this claimed area is not defined in the claim language to have a structural limitation or physical boundary and is interpreted as a region or portion) at a periphery of a main area (area or portion about 12; note that this claimed area is not defined in the claim language to have a structural limitation or physical boundary and is interpreted as a region or portion), the edge area being adjacent to the main area in a second direction (left-right direction in Fig 1) intersecting the first direction; a circuit line (12) disposed in the main area; and a support member (31,33,34 about 1S) disposed on the base film (30,BIL), the support member being adjacent to the sprocket holes (1S) in the edge area, wherein the support member (31,33,34 around 1S) includes: a support (at 31a) extending in the first direction (up-down direction in Fig 6a); and protective walls (32a) connected to the support, and the protective walls (32a) are spaced apart (see Fig 6a showing 32a spaced from next 32a by 33a) from each other with the sprocket holes (1S) disposed between the protective walls.
Regarding Claim 2, Hodono further discloses the semiconductor package film (Drawing 1,6a) of claim 1, wherein the protective walls (32a) are arranged in the first direction (up-down direction in Fig 6a), and each of the protective walls (32a) extends in the second direction (left-right direction) from the support (31a).
Regarding Claim 3, Hodono further discloses the semiconductor package film (Drawing 1,6a) of claim 2, wherein the sprocket holes (1S) are disposed between the support (31a) and the main area (area or region with 12).
Regarding Claim 4, Hodono further discloses the semiconductor package film (Drawing 1,6a) of claim 1, wherein each of the sprocket holes (1S) is partially surrounded by two protective walls (32a,32a) among the protective walls and a portion of the support (31a).
Regarding Claim 5, Hodono further discloses the semiconductor package film (Drawing 1,6a) of claim 1, wherein a width (a width between a first 32a to the next 32a in the up-down direction of Fig 6a is greater than a width of 1S in the up-down direction of Fig 6a) between protective walls (32a) adjacent to each other among the protective walls (32a) in the first direction (up-down direction) is greater than a width of one of the sprocket holes (1S) in the first direction.
Regarding Claim 6, Hodono further discloses the semiconductor package film (Drawing 1,6a) of claim 1, further comprising: a reinforcing film (BIL) attached to a lower surface of the base film (30), wherein the sprocket holes (1S) penetrate the base film (30) and the reinforcing film (BIL).
Regarding Claim 7, Hodono further discloses the semiconductor package film (Drawing 1,6a) of claim 6, wherein the reinforcing film (BIL) includes a synthetic resin material (Machine Translation page 3, paragraphs 7-13; “polyimide or polyester”).
Regarding Claim 8, Hodono further discloses the semiconductor package film (Drawing 1,6a) of claim 1, wherein the support and the protective walls include copper (Machine Translation page 3, paragraphs 7-13; “copper”).
Regarding Claim 9, Hodono discloses a semiconductor package film (Fig 1,6a) (having first (left side of Fig 1) and second (right side of Fig 1) edge areas (area about the left or right edges as seen in Fig 1; note that this claimed area is not defined in the claim language to have a structural limitation or physical boundary and is interpreted as a region or portion) and a main area (area or portion about 12; note that this claimed area is not defined in the claim language to have a structural limitation or physical boundary and is interpreted as a region or portion) which is disposed between the first and second edge areas), the semiconductor package film comprising: a base film (30,BIL) having first sprocket holes (1S on left side of Fig 1) arranged in a first direction (up-down direction of Fig 1 or 6a) in the first edge area and second sprocket holes (1S on right side of Fig 1) arranged in the first direction in the second edge area, the first and second edge areas being spaced apart (sprocket holes are spaced apart in left-right direction in Fig 1) from each other in a second direction intersecting the first direction; a first support member (31,33,34 about 1S) disposed on the base film, the first support member (31,33,34 about 1S on left side of Fig 1) being adjacent to the first sprocket holes (1S) in the first edge area; and a second support member (31,33,34 about 1S on right side of Fig 1) disposed on the base film, the second support member (31,33,34 about 1S) being adjacent Machine Translation page 3, paragraph 23; “both sides”) to the second sprocket holes (1S) in the second edge area, wherein the first support member includes a first support (at 31a) extending in the first direction (up-down direction of Fig 6a) and first protective walls (32a,32b) connected to the first support (31a), the first protective walls (32a,32b) being spaced apart (see Fig 6a showing 32a spaced from next 32a by 33a) from each other with the first sprocket holes (1S) disposed between the first protective walls (32a,32b), and the second support member includes a second support (at 31a) extending in the first direction and second protective walls (about 32a,32b) connected to the second support, the second protective walls (32a,32b) being spaced apart from each other with the second sprocket holes (1S) disposed between the second protective walls (32a,32b).
Regarding Claim 10, Hodono further discloses the semiconductor package film (Drawing 1,6a) of claim 1, wherein a width (a width between a first 32a to the next 32b in the up-down direction of Fig 6a is substantially the same as the a width of 1S in the up-down direction of Fig 6a) between protective walls (32a,32b) adjacent to each other among the protective walls in the first direction is substantially equal to a width of one of the sprocket holes (1S) in the first direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yeh (US 2009/0011186 A1) teaches of a semiconductor package film (Fig 1-2) comprising: a base film (140) having sprocket holes (120) arranged in a first direction in an edge area at a periphery of a main area (101), the edge area being adjacent to the main area in a second direction intersecting the first direction; a circuit line (110 about 101) disposed in the main area; and a support member (110 about 120) disposed on the base film, the support member being adjacent to the sprocket holes (120) in the edge area, wherein the support member includes: a support (132) extending in the first direction; and protective walls (134) connected to the support, and the protective walls are spaced apart (every third 132 would have a 120 between in the left-right direction of Fig 2) from each other with the sprocket holes (120) disposed between the protective walls (134). This reference could be used as a 102 Rejection.
Iguchi (US 2006/0054349 A1) teaches of an adhesive layer (13) between an insulating base support layer (14) and insulating substrate layer (12); this could be used in a 103 Rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896