DETAILED ACTION
This Office Action is in response to the applicant's application filed January 30th, 2024. In virtue of this communication, claims 1-20 are currently presented in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 15, 16, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et la. (US 2015/0108484 A1; hereinafter Park).
With respect to claim 1, Park teaches a display panel 100 in Figs. 1-11 comprising:
a base layer 110 including a boundary region BR and a pixel region PR (see Figs. 2, 3, and paragraphs 58-60, 77, also see Fig. 2 annotated below);
a pixel circuit (comprising first and second transistors) overlapped with the pixel region PR and including a first transistor (second transistor; including 122a, 122b, 122c, 142) including a first semiconductor pattern 122a and a first gate 142 (see Figs. 2-5, and paragraphs 60-64, 66, 89, also see Fig. 2 annotated below); and
a plurality of insulating layers (150, 160), wherein an opening OP defined in the plurality of insulating layers (150, 160) corresponds to the boundary region BR (see Figs. 2-10 and paragraphs 65, 69, 71, 72, 95, 106, 109, 110, also see Fig. 2 annotated below),
wherein a first insulating layer 160 of the plurality of insulating layers (150, 160) covers the first gate 142, and a groove (GV, 166) defined in the first insulating layer 160 is spaced apart from the opening OP (see Figs. 2-9 and paragraphs 65, 69, 71, 72, 95, 100, 106, 109, 110, also see Fig. 2 annotated below), and
wherein the groove (GV, 166) is formed through a portion of the first insulating layer 160 (see Figs. 2-9 and paragraphs 65, 69, 71, 72, 95, 100, 106, 109, 110, also see Fig. 2 annotated below).
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With respect to claim 2, Park teaches the display panel of claim 1, wherein the groove GV is overlapped by the first semiconductor pattern 122a (see Figs. 2, 9, and paragraphs 89, 106-110, also see Fig. 2 annotated above).
With respect to claim 3, Park teaches the display panel of claim 1, wherein the opening OP is formed through the plurality of insulating layers (150, 160) (see Figs. 2, 9, and paragraphs 69, 100, 106, 110, also see Fig. 2 annotated above).
With respect to claim 4, Park teaches the display panel of claim 1, wherein a depth of the opening OP is greater than a depth of the groove (GV, 166), in a thickness direction (see Figs. 2, 9, and paragraphs 69, 100, 106, 110, also see Fig. 2 annotated above).
With respect to claim 5, Park teaches the display panel of claim 1, further comprising: a metal layer 140 disposed at a layer 130 the same as a layer 130 at which the first gate 142 is disposed (see Figs. 2 and paragraphs 61, 64, 65).
With respect to claim 15, Park teaches a method for manufacturing a display panel 100 in Figs. 1-11, the method comprising:
preparing a base layer 110 including a boundary region BR and a pixel region PR (see Figs. 2, 3, and paragraphs 58-60, 77, also see Fig. 2 annotated below);
forming a transistor (second transistor; including 122a, 122b, 122c, 142) overlapped with the pixel region PR and including a semiconductor pattern 122a and a gate 142 (see Figs. 2-5, and paragraphs 60-64, 66, 89, also see Fig. 2 annotated below); and
forming an insulating layer (150, 160) covering the gate 142 (see Figs. 2-9 and paragraphs 65, 69, 71, 72, 95, 100, 106, 109, 110, also see Fig. 2 annotated below),
wherein an opening OP corresponding to the boundary region BR and a groove (GV, 166) spaced apart from the opening OP are formed in the forming of the insulating layer (150, 160) (see Figs. 2-9 and paragraphs 65, 69, 71, 72, 95, 100, 106, 109, 110, also see Fig. 2 annotated below), and
wherein the groove (GV, 166) is formed through a portion of the insulating layer 160 (see Figs. 2-9 and paragraphs 65, 69, 71, 72, 95, 100, 106, 109, 110, also see Fig. 2 annotated below).
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With respect to claim 16, Park teaches the method of claim 15, further comprising: forming a metal layer 152 overlapped with the semiconductor pattern 122a, after forming the transistor (second transistor; including 122a, 122b, 122c, 142) and before forming the insulating layer (150, 160) (see Figs. 2-5 and paragraphs 61, 65, 85, 86, 88, 92).
With respect to claim 18, Park teaches the method of claim 15, further comprising: etching the insulating layer (150, 160), wherein the groove GV and the opening OP are formed by etching the insulating layer (150, 160), and wherein a first etching depth associated with forming the groove GV is less than a second etching depth associated with forming the opening OP (see Figs. 2-10 and paragraphs 65, 69, 71, 72, 95, 100, 106, 109, 110, also see Fig. 2 annotated above),
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 9, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et la. (US 2015/0108484 A1; hereinafter Park) in view of Cai et al. (US 2021/0249449 A1; hereinafter Cai).
With respect to claim 8, Park discloses the display panel of claim 1, wherein the pixel circuit further comprises: a second transistor (first transistor; including 120a, 120b, 120c, 140) including a second semiconductor pattern 120a and a second gate 140 (see Figs. 2-5 and paragraphs 61, 66, and 89).
Park does not disclose wherein the second transistor is disposed at a layer different from a layer at which the first transistor is disposed.
Cai disclose a display panel in at least Figs. 17 and 27 wherein a second transistor 12 is disposed at a layer different from a layer at which a first transistor 26 is disposed (see Figs. 17 and 27 and paragraphs 107, 108, 144, 145).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the display panel of Park the second transistor would be disposed at a layer different from a layer at which the first transistor is disposed as taught by Cai because in this manner, the second active layer 261 can be protected from being damaged when the first active layer 121 is processed at a high temperature (see Cai: paragraph 108).
With respect to claim 9, the combination of Park and Cai discloses the display panel of claim 8, wherein: the first semiconductor pattern 261 includes an oxide semiconductor, and the second semiconductor pattern 121 includes a silicon semiconductor (see Cai: Figs. 17, 27, and paragraphs 107, 108).
With respect to claim 20, Park discloses the method of claim 15.
Park does not explicitly disclose wherein the semiconductor pattern comprises an oxide semiconductor.
Cai discloses a method in at least Figs. 17 and 27 wherein a semiconductor pattern 261 comprises an oxide semiconductor (see Figs. 17, 27, and paragraphs 107, 108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor pattern of Park would comprise an oxide semiconductor as taught by Cai because oxide semiconductor patterns are well known in the art and it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07).
Claims 10, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Park et la. (US 2015/0108484 A1; hereinafter Park) in view of Kim et al. (US 2020/0303479 A1; hereinafter Kim).
With respect to claim 10, Park discloses a display panel 100 in Figs. 1-11 comprising:
a base layer 110 including a boundary region BR and a pixel region PR (see Figs. 2, 3, and paragraphs 58-60, 77, also see Fig. 2 annotated below);
a pixel circuit (comprising first and second transistors) overlapped with the pixel region PR and including a first transistor (second transistor; including 122a, 122b, 122c, 142) including a first semiconductor pattern 122a and a first gate 142 (see Figs. 2-5, and paragraphs 60-64, 66, 89, also see Fig. 2 annotated below); and
a plurality of insulating layers (150, 160), wherein an opening OP defined in the plurality of insulating layers (150, 160) corresponds to the boundary region BR (see Figs. 2-10 and paragraphs 65, 69, 71, 72, 95, 106, 109, 110, also see Fig. 2 annotated below),
wherein [there is] a distance between the first semiconductor pattern 122a and the opening OP in a direction perpendicular to a thickness direction (see Figs. 2-10 and paragraphs 69, 109-110; note separation between OP and 122a, also see Fig. 2 annotated below).
Park does not explicitly disclose wherein the distance is 5 μm or more and 70 μm or less.
Kim discloses a display panel in at least Figs. 1-5A wherein a width of an opening is 5 μm or more and 70 μm or less (see Fig. 5A and paragraphs 93, 107, 108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a distance between the first semiconductor pattern and the opening would be 5 µm or more and 70 µm or less in a direction perpendicular to a thickness direction because the combination of Park and Kim disclose the general conditions and scale of the claim and it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only ordinary skill in the art (see MPEP 2144.05 I). The dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious (see MPEP 2144.04 IV B).
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With respect to claim 11, the combination of Park and Kim discloses the display panel of claim 10, wherein the opening OP is formed through the plurality of insulating layers (150, 160) (see Park: Figs. 2, 9, and paragraphs 69, 100, 106, 110, also see Fig. 2 annotated above).
With respect to claim 13, the combination of Park and Kim discloses the display panel of claim 10, further comprising: a barrier layer 101 disposed on the base layer 110, wherein the barrier layer 101 is exposed by the opening GR (see Kim: Figs. 5A, 5B, 6D, and paragraphs 85, 87, 104, 105, 182). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the display panel of the combination of Park and Kim would further comprise a barrier layer disposed on the base layer, wherein the barrier layer is exposed by the opening as taught by Kim. The barrier layer 101 may prevent or minimize impurities, such as impurities from the substrate 110, from permeating into the semiconductor layer (see Kim: paragraph 105).
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Park et la. (US 2015/0108484 A1; hereinafter Park) and Kim et al. (US 2020/0303479 A1; hereinafter Kim) as applied to claim 10 above, and further in view of Cai et al. (US 2021/0249449 A1; hereinafter Cai).
With respect to claim 12, the combination of Park and Kim discloses the display panel of claim 10.
The combination does not disclose wherein the first semiconductor pattern includes an oxide semiconductor.
Cai discloses a display panel in at least Figs. 17 and 27 wherein a first semiconductor pattern 261 includes an oxide semiconductor (see Figs. 17, 27, and paragraphs 107, 108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first semiconductor pattern of the combination of Park and Kim would include an oxide semiconductor as taught by Cai because oxide semiconductor patterns are well known in the art and it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07).
With respect to claim 14, the combination of Park and Kim discloses the display panel of claim 10, wherein the pixel circuit (comprising first and second transistors) comprises: a second transistor (first transistor; including 120a, 120b, 120c, 140) including a second semiconductor pattern 120a and a second gate 140 (see Figs. 2-5 and paragraphs 61, 66, and 89).
The combination does not disclose wherein the second transistor is disposed at a layer different from a layer at which the first transistor is disposed, and wherein the second semiconductor pattern includes a silicon semiconductor.
Cai discloses a display panel in at least Figs. 17 and 27 wherein a second transistor 12 is disposed at a layer different from a layer at which the first transistor 26 is disposed, and wherein a second semiconductor pattern 121 includes a silicon semiconductor (see Figs. 17 and 27 and paragraphs 107, 108, 144, 145).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in the display panel of the combination of Park and Kim the second transistor would be disposed at a layer different from a layer at which the first transistor is disposed, and wherein the second semiconductor pattern would include a silicon semiconductor as taught by Cai because in this manner, the second active layer 261 can be protected from being damaged when the first active layer 121 is processed at a high temperature (see Cai: paragraph 108).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Park et la. (US 2015/0108484 A1; hereinafter Park).
With respect to claim 17, Park discloses the method of claim 16.
Park does not explicitly disclose wherein the metal layer comprises at least one of aluminum (Al), molybdenum (Mo), titanium (Ti), and indium gallium zinc oxide (IGZO).
However, Park discloses that the metals of the first conductive layer used to make the first and second gate electrodes 140 and 142 may include aluminum (Al), chromium (Cr), nickel (Ni), molybdenum (Mo), tungsten (W), magnesium (Mg) (see paragraphs 85, 86). One of ordinary skill in the art hoping to reduce the cost of manufacturing selects the cheapest combination of materials for a semiconductor device and further reduces cost and manufacturing time by having all of the conductive layers of the device made of the same material (see MPEP 2144 I).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the metal layer 152 of Park would comprises at least one of aluminum (Al), molybdenum (Mo), titanium (Ti), and indium gallium zinc oxide (IGZO) because the other conductive layers of Park are made of those same materials because the cost and time of manufacturing are reduced when the plurality of patterns of the metal layer are all made of the same material (see MPEP 2144 I).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Park et la. (US 2015/0108484 A1; hereinafter Park) in view of Choi et al. (US 2017/0237025 A1; hereinafter Choi).
With respect to claim 19, Park discloses the method of claim 15.
Park does not disclose wherein the forming of the groove and the opening is based on a half tone mask.
Choi discloses a method for manufacturing a display panel wherein a forming of a groove and an opening is based on a half tone mask (see paragraphs 175, 176, 255).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that in method of Park the forming of the groove and the opening would be based on a half tone mask as taught by Choi because etching with a half tone mask is well known in the art and such a method allows a certain part may be etched (removed) more than other parts (see Choi: paragraph 176. Also see MPEP 2144 I).
Allowable Subject Matter
Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not disclose or fairly suggest the display panel of claim 5, wherein a surface of the metal layer is exposed by the groove as called for in claim 6 (claim 7 depends from claim 6).
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a similar display panel: US 10573704 B2 and US 20210336164 A1.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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