DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 5/26/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (US PG Pub 2024/0387426, hereinafter Farooq).
Regarding claim 1, figures 2A-2D of Farooq disclose a method for forming a chip package structure, comprising:
providing a first wiring substrate (300) comprising a first dielectric layer (310/330) and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a conductive layer (311) and a seed layer between the conductive layer and the first dielectric layer, the seed layer comprises an adhesive film (¶ 33) and a conductive film (321), the adhesive film comprises a first metal element (¶ 33), the conductive film comprises a second metal element and a third metal element (¶ 35);
providing a second wiring substrate (400) over the first wiring substrate, wherein the second wiring substrate comprises a second dielectric layer (410/430) and a second bonding pad (421) embedded in the second dielectric layer; and
performing an annealing process (¶ 38) to bond the second bonding pad to the first bonding pad.
Regarding the limitations “the second metal element has a greater conductivity than the first metal element and the third metal element, and the third metal element reacts more readily with oxygen than the second metal element” and “wherein a metal oxide layer is formed between the seed layer and the first dielectric layer after the annealing process, and the metal oxide layer comprises the first metal element and the third metal element”, the prior art teaches the same method with the same materials as disclosed in applicants’ specification (see additional claim rejections below) and it is taken that this would produce similar results as claimed.
Regarding claim 2, figures 2A-2D of Farooq disclose the third metal element comprises cobalt or manganese (¶ 35).
Regarding claim 3, figures 2A-2D of Farooq disclose the first metal element comprises tantalum or titanium (¶ 33).
Regarding claim 4, figures 2A-2D of Farooq disclose the second metal element comprises copper (¶ 35).
Regarding claim 5, figures 2A-2D of Farooq disclose teaches the same method with the same materials as disclosed in applicants’ specification and it is taken that this would produce similar results as claimed.
However, it would have been obvious to perform the anneal such that the metal oxide layer thickness is within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 6, figures 2A-2D of Farooq disclose teaches the same method with the same materials as disclosed in applicants’ specification and it is taken that this would produce similar results as claimed.
However, it would have been obvious to perform the anneal such that the metal oxide layer thickness is within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 7, figures 2A-2D of Farooq disclose a portion of the metal oxide layer (441) is between the seed layer and the second dielectric layer (410).
Regarding claim 8, figures 2A-2D of Farooq disclose the metal oxide layer is in direct contact with the adhesive film and the first dielectric layer. Note that Farooq disclose teaches the same method with the same materials as disclosed in applicants’ specification and it is taken that this would produce similar results as claimed.
Regarding claim 9, figures 2A-2D of Farooq disclose the metal oxide layer (441) is in direct contact with the second dielectric layer (410).
Regarding claim 10, figures 2A-2D of Farooq disclose the metal oxide layer (441) is in direct contact with the second bonding pad (421).
Regarding claim 11, figures 2A-2D of Farooq disclose bonding the first dielectric layer (310/330) to the second dielectric layer (410/430) during bonding the first bonding pad (321) to the second bonding pad (421).
Regarding claim 12, figures 2A-2D of Farooq disclose a method for forming a chip package structure, comprising:
providing a first wiring substrate (300) comprising a first dielectric layer (310/330) and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a conductive layer (311) and a seed layer (321) between the conductive layer and the first dielectric layer;
providing a second wiring substrate (400) over the first wiring substrate, wherein the second wiring substrate comprises a second dielectric layer (410/430) and a second bonding pad (411) embedded in the second dielectric layer; and
bonding the second bonding pad to the first bonding pad using an annealing process (¶ 38).
Regarding the limitations “wherein a metal oxide layer is formed between the seed layer and the first dielectric layer after the annealing process, and a first density of the metal oxide layer is greater than a second density of the seed layer”, the prior art teaches the same method with the same materials and it is taken that this would produce similar results as claimed.
Regarding claim 13, Farooq does not explicitly disclose the seed layer (321) comprises cobalt and manganese.
However, it would have been obvious to use a seed layer comprising cobalt and manganese for the purpose of selecting a suitable and well known material for seed layers.
Regarding the limitations “the metal oxide layer comprises a first film and a second film, the first film is between the seed layer and the second film, and the first film has a higher cobalt concentration than the second film”, the prior art teaches the same method with the same materials and it is taken that this would produce similar results as claimed.
Regarding claim 14, the prior art teaches the same method with the same materials and it is taken that this would produce similar results as claimed.
Regarding claim 15, figures 2A-2D of Farooq disclose the metal oxide layer (441) extends into the second dielectric layer (410/430).
Regarding claim 21, figures 2A-2D of Farooq disclose a method for forming a chip package structure, comprising:
providing a first wiring substrate (300) comprising a first dielectric layer (310/330) and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first conductive layer (311) and a first seed layer (321) between the first conductive layer and the first dielectric layer;
providing a second wiring substrate (400) over the first wiring substrate, wherein the second wiring substrate comprises a second dielectric layer (410/430) and a second bonding pad (411) embedded in the second dielectric layer; and
bonding the second bonding pad to the first bonding pad using an annealing process (¶ 38), wherein a first metal oxide layer (441) is formed between the first seed layer and the second dielectric layer after the annealing process.
Regarding the limitations “wherein a first metal oxide layer is formed between the first seed layer and the first dielectric layer”, the prior art teaches the same method with the same materials and it is taken that this would produce similar results as claimed.
Regarding claim 22, figures 2A-2D of Farooq disclose a first portion of the first metal oxide layer (441) extends into the second dielectric layer (410/430).
Regarding claim 23, figures 2A-2D of Farooq disclose the first portion of the first metal oxide (441) layer covers a top surface of the first seed layer, and the top surface faces the second dielectric layer (410/430).
Regarding claim 24, figures 2A-2D of Farooq disclose the second bonding pad comprises a second conductive layer (411) and a second seed layer (421) between the second conductive layer and the second dielectric layer (410/430).
Regarding the limitations “a second metal oxide layer is formed between the second seed layer and the second dielectric layer after the annealing process”, the prior art teaches the same method with the same materials and it is taken that this would produce similar results as claimed.
Regarding claim 25, figures 2A-2D of Farooq disclose a second portion of the second metal oxide layer (342) extends into the first dielectric layer (310/330).
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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