Prosecution Insights
Last updated: July 17, 2026
Application No. 18/427,063

DEVICE WITH INNER AND OUTER SPACERS

Non-Final OA §102§103
Filed
Jan 30, 2024
Examiner
HENRY, CALEB E
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Globalfoundries U.s. Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1082 granted / 1248 resolved
+18.7% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
1285
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
71.9%
+31.9% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1248 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-19 in the reply filed on 5/19/2026 is acknowledged. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 4 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Koirala (20240204059). Regarding claim 1, Koirala teaches a structure (please see fig. 8C) comprising: a gate structure (810) on a semiconductor substrate (812); a gate metal (828, par. 60) connecting to the gate structure; inner sidewall spacers (822) contacting and surrounding the gate metal; a passivation layer (860, par/ 98) on the inner sidewall spacers; and outer sidewall spacers (872) on the passivation layer and adjacent to sides of the gate structure. Regarding claim 4, Koirala teaches a structure of claim 1, wherein the passivation layer is a nitride material (par. 98) between the inner sidewall spacers and the outer sidewall spacers (see fig. 8C). Regarding claim 11, Koirala teaches a structure of claim 1, further comprising a field plate connecting to the gate metal above the outer sidewall spacers on a drain side (par. 59-61). Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Puglisi (20120261720). Regarding claim 1, Puglisi teaches a structure (fig. 2I) comprising: a gate structure (22) on a semiconductor substrate (812); a gate metal (24G; par. 130) connecting to the gate structure; inner sidewall spacers (28) contacting and surrounding the gate metal; a passivation layer (26A/26B) on the inner sidewall spacers; and outer sidewall spacers (fig. 2D: 25A/25B) on the passivation layer and adjacent to sides of the gate structure. Regarding claim 6, Puglisi teaches a structure of claim 1, wherein the gate metal extends over an outside of the outer sidewall spacers on a drain side (please see fig. 2I). Claims 1-8, 11-17 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Toh (10790366). Regarding claim 1, Toh teaches a structure (fig. 4) comprising: a gate structure (please see fig. 4) on a semiconductor substrate (103); a gate metal (203) connecting to the gate structure; inner sidewall spacers (305/309) contacting and surrounding the gate metal; a passivation layer (307) on the inner sidewall spacers; and outer sidewall spacers (301) on the passivation layer and adjacent to sides of the gate structure. Regarding claim 2, Toh teaches a structure of claim 1, wherein the gate structure comprises p-GaN material (Toh teaches that 101 can be doped with Boron or Indium). Regarding claim 3, Toh teaches a structure of claim 2, wherein the inner sidewall spacers and the outer sidewall spacers comprise dielectric material (Toh teaches these to be oxides and nitrides). Regarding claim 4, Toh teaches a structure of claim 1, wherein the passivation layer is a nitride material between the inner sidewall spacers and the outer sidewall spacers (Toh teaches these to be oxides and nitrides). Regarding claim 5, Toh teaches a structure of claim 1, wherein the outer sidewall spacers surround the gate structure and the gate metal and the inner sidewall spacers are above the gate structure. Regarding claim 6, Toh teaches a structure of claim 1, wherein the gate metal extends over an outside of the outer sidewall spacers on a drain side (). Regarding claim 7, Toh teaches a structure of claim 6, further comprising a field plate (403) connecting to the gate metal on the outside the outer sidewall spacers on the drain side (please see fig. 4). Regarding claim 8, Toh teaches a structure of claim 7, wherein the field plate abuts the outer sidewall spacers on the drain side (see fig. 4). Regarding claim 11, Toh teaches a structure of claim 1, further comprising a field plate (403) connecting to the gate metal above the outer sidewall spacers on a drain side. Regarding claim 12, Toh teaches a structure (please see fig. 4), comprising: a device over a wide-bandgap semiconductor layer (101 can be GaN); a passivation layer (307) on the device; a gate metal (203) connecting to the device; inner sidewall spacers (305/309) on the passivation layer and surrounding the gate metal; a liner (401) over the inner sidewall spacers; and outer sidewall spacers (301) on the liner and surrounding the device. Regarding claim 13, Toh teaches a structure of claim 12, wherein the device comprises a p-GaN gate structure (Toh teaches that 101 can be doped with Boron or Indium). Regarding claim 14, Toh teaches a structure of claim 12, wherein the outer sidewall spacers surround the gate metal (please see fig. 4). Regarding claim 15, Toh teaches a structure of claim 12, wherein the gate metal extends over an outer side of the outer sidewall spacers on a drain side and extends to liner (please see fig. 4). Regarding claim 16, Toh teaches a structure of claim 15, further comprising a field plate (403) connecting to the gate metal. Regarding claim 17, Toh teaches a structure of claim 16, wherein the field plate abuts the outer sidewall spacers and connects to the gate metal. Regarding claim 19, Toh teaches a structure of claim 12, wherein the inner sidewall spacers are on an inner portion of the passivation layer, the outer sidewall spacers are on an outer portion of the passivation layer, and the gate metal is surrounded by the inner sidewall spacers, the passivation layer and the outer sidewall spacers (please see fig. 4). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Bajaj (20230197840). PNG media_image1.png 592 760 media_image1.png Greyscale Regarding claim 1, Bajaj teaches a structure comprising: a gate structure (110) on a semiconductor substrate (102); a gate metal (104; par. 35) connecting to the gate structure; inner sidewall spacers (par. 81 teaches that the gate stack seen in fig, 2A, 200, can have opposing sides covered with 4 pairs of spacers) contacting and surrounding the gate metal; a passivation layer (114) on the inner sidewall spacers; and outer sidewall spacers (par. 81 teaches that the gate stack seen in fig, 2A, 200, can have opposing sides covered with 4 pairs of spacers) on the passivation layer and adjacent to sides of the gate structure. Please note that multiple embodiments of prior art are used above. It would have been obvious to a PHOSITA, at the time of filing to utilize these embodiments in combination since are related to similar fields of endeavor. Further, the use of sidewall spacers is known to help in achieving smaller, more precise gate structures. Regarding claim 5, Bajaj teaches a structure of claim 1, wherein the outer sidewall spacers surround the gate structure and the gate metal and the inner sidewall spacers are above the gate structure (please see rejection for claim 1 above ). Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Bajaj (20230197840). PNG media_image1.png 592 760 media_image1.png Greyscale Regarding claim 1, Bajaj teaches a structure comprising: a gate structure (110) on a semiconductor substrate (102); a gate metal (116; par. 27) connecting to the gate structure; inner sidewall spacers (par. 81 teaches that the gate stack seen in fig, 2A, 200, can have opposing sides covered with 4 pairs of spacers) contacting and surrounding the gate metal; a passivation layer (114) on the inner sidewall spacers; and outer sidewall spacers (par. 81 teaches that the gate stack seen in fig, 2A, 200, can have opposing sides covered with 4 pairs of spacers) on the passivation layer and adjacent to sides of the gate structure. Please note that multiple embodiments of prior art are used above. It would have been obvious to a PHOSITA, at the time of filing to utilize these embodiments in combination since are related to similar fields of endeavor. Further, the use of sidewall spacers is known to help in achieving smaller, more precise gate structures. Regarding claim 2, Bajaj teaches a structure of claim 1, wherein the gate structure comprises p-GaN material (par. 18). Regarding claim 3, Bajaj teaches a structure of claim 2, wherein the inner sidewall spacers and the outer sidewall spacers comprise dielectric material (par. 81). Allowable Subject Matter Claim 9 (please note dependencies) objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 10 is objected to based on its dependency on claim 9. Claim 18 (please note dependencies) objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEB E HENRY/ Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Jan 30, 2024
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+6.1%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1248 resolved cases by this examiner. Grant probability derived from career allowance rate.

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