DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
In response to applicant’s remarks and amendments, all claims 1-20 are examined herein.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 11-13 & 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yu e al (US 2020/0118908).
The applied reference has a common assignee (Taiwan semiconductor) with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding independent claims 11 & 18, Yu (Fig. 9) clearly shows a semiconductor structure comprising following claimed components:
a memory cell (located in the cell array M1 on top/tier 3 level as example) having a first boundary, a logic cell (located in the logic array L1 on top/tier 3 level as example) having a second boundary, and an interconnect structure (see the two metal/conductive layers 40 & balls 42, disposed over the memory cell arrays M1 and the logic cell arrays L1), wherein at least the Fig. 9 additionally shows the interconnect structure further includes:
metal tracks 40 carrying a signal line (see illustration below) also extending continuously along a first direction from inside the second boundary of the logic cell and into the first boundary of the memory cell,
a computational element disposed within the first boundary of the memory cell in a tier 3 level or top view of the semiconductor structure. For example, para [0015] stated that “… the term “compute-in-memory” (or CIM) refers to the structure that logic dies, which perform computing functions, are immersed in the memory dies that logic dies access, etc.”, which suggests that the memory dies can calculate/perform logic functions (OR, XOR & AND, etc.) for the data bits in each cell, and the logic dies will access or route its results out to the user as conventional knowledge to a skilled person in this art.
[AltContent: arrow][AltContent: arrow][AltContent: textbox (A top/metal tracks 40 carrying signal lines crossing from inside logic/L1 boundary into memory/M1 boundary)]
[AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Memory die = M1)][AltContent: arrow][AltContent: textbox (Logic die = L1)]
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[AltContent: textbox (Vertical boundaries for either L1 or M1 dies = plurality of shaded vertical areas divided between dies
Logic die L1)]
Claim 12, para [0017] mentions memory dies can include either choices of SRAM cells and/or DRAM cells with capacitor, and thus MIM-type capacitor for DRAM cells could also be used, etc.
Claim 13, each SRAM cell has two output nodes and either output node could be used to transfer data to the logic dies.
Claim 18, Fig. 9 above additionally shows that the two of metal tracks 40 disposed over logic dies are also similarly formed and aligned with the two metal tracks 40 disposed over the memory dies
Claims 19-20, the metal tracks 40 above could also carry other signals for communication its data with all the adjacent the logic dies, which all these signal lines could be word lines, bit lines, ground, or power writings, etc., since all of these lines are also considered as conventional design for a skilled person in this art as well.
Allowable Subject Matter
3. The following claims contain allowable subject matter for the following reasons:
- Claim group 1-10 recite a novel semiconductor memory structure which a memory cell connected to a signal line, a first voltage line for receiving a power supply voltage, and a second voltage line for receiving an electric ground voltage; a logic cell configured to provide logic function to the memory cell, wherein the logic cell is connected to the signal line, the first voltage line, and the second voltage line; and a transition region extending from a first boundary of the memory cell to a second boundary of the logic cell; and an interconnect structure disposed over the memory cell and the logic cell, wherein the interconnect structure includes the signal line, the first voltage line, and the second voltage line located in a same metal line layer of the interconnect structure, and wherein the signal line extends from inside the second boundary of the logic cell and into the first boundary of the memory cell, and wherein the transition region includes one or more functional transistors electrically coupled to the memory cell.
Additionally, all the dependent claims 14-17 are objected as being depending upon their parent/rejected claim 11, but they also tentatively contain other novel limitations not seen by prior arts elsewhere at this time:
Claim 14 recites the memory cell includes first and second active regions each extending continuously along the first direction from inside the first boundary of the memory cell and into the second boundary of the logic cell.
Claim 15 recites that a contour of the computational element overlaps with the first and second active regions from the top view of the semiconductor structure.
Claim 16 recites that a contour of the computational element is free of overlapping with the first and second active regions from the top view of the semiconductor structure.
Claim 17 recites usage of a transition region stacked between the memory cell and the logic cell along the first direction, wherein the transition region includes functional transistors electrically coupled to the memory cel
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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