DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 6/22/26. Claims 1-15 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, and 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US PGPub 2023/0055202, hereinafter referred to as “Wang”) in view of Hwang et al. (US PGPub 2015/0126013, hereinafter referred to as “Hwang”) in further view of Liang et al. (US PGPub 2014/0183642, hereinafter referred to as “Liang”).
Wang discloses the semiconductor method substantially as claimed. See figures 1-14 and corresponding text, where Wang shows, in claim 1, a manufacturing method of a semiconductor structure, comprising:
providing a bit line structure (103) and a trench (110) adjacent to the bit line structure (103), wherein a first spacer (107) is disposed on a sidewall and a top surface of the bit line structure (103), and a second spacer (108a) is disposed on a sidewall and a top surface of the first spacer (107); (figure 9; [0037-0045])
removing a portion of the second spacer (108a) to expose a top surface of the first spacer (107) and forming an etched second spacer (108), wherein the etched second spacer (108) expose a bottom surface of the trench (110) (the examiner views that the trench is formed after the etched spacer is formed, thus meets the bottom surface exposure of the trench limitation); (figures 9-13; [0046-0073])
forming a third spacer (109) on a sidewall of the etched second spacer (108), wherein the third spacer (109) covers a top surface of the etched second spacer (figures 12-14; [0062-0073], [0075-0090]).
Wang fails to show, in claim 1, forming a photoresist layer in the trench, wherein the photoresist layer has a height that is smaller than a depth of the trench; removing the photoresist layer to expose a bottom surface of the trench.
Hwang teaches, in claim 1, forming a similar device that includes the use of a photoresist film pattern to form first openings ([0049-0055]). In addition, Hwang provides the advantages of reducing parasitic capacitance ([0216]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention, to incorporate forming a photoresist layer in the trench, wherein the photoresist layer has a height that is smaller than a depth of the trench; removing the photoresist layer to expose a bottom surface of the trench, in the method of Wang, according to the teachings of Hwang, with the motivation of reducing parasitic capacitance.
However, Wang in view of Hwang fails to explicitly teach, in claim 1, wherein a portion of the third spacer that covers the top surface of the etched second spacer serves as a butter layer to protect the etched second spacer.
Liang teaches, At paragraph [0022] and [0033], detailing an inner spacer 132, an outer spacer 142, and a buffer layer in between – three protective layers essentially. The outer spacer purpose is for etch optimization, the buffer layer for etch selectivity and protection from over etching.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate, wherein a portion of the third spacer that covers the top surface of the etched second spacer serves as a butter layer to protect the etched second spacer, in the method of Wang in view of Hwang, with the motivation of outer spacer purpose is for etch optimization, the buffer layer for etch selectivity and protection from over etching.
Wang shows, in claim 11, a manufacturing method of a semiconductor structure, comprising:
providing a bit line structure (103) and a trench (110) adjacent to the bit line structure, wherein a first spacer (107) is disposed on a sidewall and a top surface of the bit line structure (103), and a second spacer (108a) is disposed on a sidewall and a top surface of the first spacer (107);
removing a portion of the second spacer to expose a top surface of the first spacer and forming an etched second spacer (108);
expose a bottom surface of the trench (110);
forming a third spacer (109) on a sidewall of the etched second spacer, wherein the third spacer covers a top surface of the etched second spacer (figures 9-14; [0062-0070]).
Wang fails to show, in claim 11, forming a photoresist layer in the trench, wherein the photoresist layer comprises carbon and hydrogen, wherein the photoresist layer has a height that is smaller than a depth of the trench; removing the photoresist layer to expose a bottom surface of the trench.
Hwang teaches, in claim 11, forming a similar device that includes the use of a photoresist film pattern to form first openings ([0049-0055]). In addition, Hwang provides the advantages of reducing parasitic capacitance ([0216]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention, to incorporate forming a photoresist layer in the trench, wherein the photoresist layer comprises carbon and hydrogen, wherein the photoresist layer has a height that is smaller than a depth of the trench; removing the photoresist layer to expose a bottom surface of the trench, in the method of Wang, according to the teachings of Hwang, with the motivation of reducing parasitic capacitance.
However, Wang in view of Hwang fails to explicitly teach, in claim 11, wherein a portion of the third spacer that covers the top surface of the etched second spacer serves as a butter layer to protect the etched second spacer.
Liang teaches, At paragraph [0022] and [0033], detailing an inner spacer 132, an outer spacer 142, and a buffer layer in between – three protective layers essentially. The outer spacer purpose is for etch optimization, the buffer layer for etch selectivity and protection from over etching.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate, wherein a portion of the third spacer that covers the top surface of the etched second spacer serves as a butter layer to protect the etched second spacer, in the method of Wang in view of Hwang, with the motivation of outer spacer purpose is for etch optimization, the buffer layer for etch selectivity and protection from over etching.
Wang in view Hwang in further view of Liang teaches, in claim 12, wherein the first spacer and the third spacer comprise nitride ([0057], Hwang).
Wang in view Hwang in further view of Liang teaches, in claim 13, wherein the second spacer comprises oxide ([0057], Hwang).
Wang in view Hwang in further view of Liang teaches, in claim 14, wherein the portion of the second spacer is removed by a wet etching process ([0076], Hwang).
Wang in view Hwang in further view of Liang teaches, in claim 15, wherein the photoresist layer is removed by a stripping process ([0049-0055], HwangwH).
Allowable Subject Matter
Claims 2-10 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 August 26, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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