DETAILED ACTION
This Office action is in response to the RCE filed 28 October 2025. Claims 1-13, 15-19, and 21-22 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7 October 2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 18-19 have been considered but are moot because the grounds of rejection have been modified in response to Applicant’s amendments to the claims. The amended limitations are addressed by the modified grounds of rejection below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 18, 19, and 22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2020/0219925 A1 to Jang (hereinafter “Jang”).
Regarding independent claim 18, Jang (Fig. 5) discloses a method for forming an integrated chip, comprising:
forming a first photodetector PD3 (¶ 0073) and a second photodetector PD4 (¶ 0073) in a semiconductor substrate 100 (¶¶ 0074-75);
forming an isolation structure 170 (¶ 0073) in the semiconductor substrate, wherein the isolation structure comprises an isolation segment (segment of 170 between PD3 and PD4) continuously vertically extending from a first point at a top surface 100a (¶ 0074) of the semiconductor substrate to a second point below the top surface of the semiconductor substrate (Fig. 5), wherein the isolation segment is spaced laterally between the first photodetector PD3 and the second photodetector PD4 and comprises a first material (¶ 0089) different from a second material (¶ 0075) of the semiconductor substrate 100;
and forming a gate structure SFG (¶ 0073) over the first and second photodetectors PD3/PD4 and on the isolation segment (segment of 170), wherein a first distance between a top surface of the isolation segment and a bottom surface of the gate structure SFG (segment of 170 contacts SFG) is less than a second distance between the top surface of the isolation segment and the first photodetector PD3 (Fig. 5).
Regarding claim 19, Jang (Fig. 5) discloses the method of claim 18, wherein forming the isolation structure comprises: etching the semiconductor substrate to form a trench extending into the semiconductor substrate (¶ 0080), wherein the top surface of the semiconductor substrate 100 is discontinuous in a region between the first and second photodetectors PD3/PD4 (Fig. 5); and depositing the first material in the trench (¶ 0082).
Regarding claim 22, Jang (Fig. 5) discloses The method of claim 18 wherein the gate structure SFG contacts the top surface of the isolation segment (segment of 170 under SFG).
Allowable Subject Matter
Claims 1-9 are allowed.
Independent claim 1 recites, inter alia, the first and second source/drain regions are spaced between and laterally offset from the pair of sidewalls, wherein the first source/drain region is laterally offset from the second source/drain region in the first direction, wherein the first source/drain region and the second source/drain region both intersect a plane parallel to the first sidewall. These limitations, in combination with the remaining limitations of the independent claim, are not anticipated or rendered obvious by the prior art. Claims 2-9 depend from independent claim 1.
Claims 10-13 and 15-17 are allowed for the reasons as set forth in the Final Rejection mailed 6 August 2025.
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, for the reasons as set forth in the Final Rejection mailed 6 August 2025.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2020/0176500 A1 to Sze et al. disclosing an image sensor with a transfer transistor over the semiconductor substrate.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
CANDICE Y. CHAN
Examiner
Art Unit 2813
20 December 2025