DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06/17/2026 have been fully considered but they are not moot in view of the new grounds of rejection as necessitated by Applicant’s claim amendments as detailed below.
Applicant’s amended title overcomes the previous specification objection the title.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3,5-11,13,15-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0134525 A1 to Ma et al., “Ma”, in view of US 2024/0079315 A1 to WANG et al., “Wang”.
Regarding claim 1, Ma discloses a semiconductor device (FIG. 8), comprising:
a conductive layer (23, ¶ [0024],[0033]) having a trench (spaces between 29);
a landing pad (45, ¶ [0032],[0033]) filled in the trench;
a capacitor (138, ¶ [0053],[0054]) disposed over the landing pad; and
an interlayer contact (114 which becomes 118, ¶ [0046],[0047]) connected between the landing pad (45) and the capacitor (138), wherein a width of a top of the interlayer contact (upper 114/118) is greater than a width of the capacitor (width of 132).
Ma fails to clearly teach wherein a bottom surface of the interlayer contact (114 which becomes 118) is lower than a top surface of the landing pad with a distance, and wherein the width of a portion of the interlayer contact in a recessed portion of the landing pad tapers downward.
Wang teaches (e.g. Fig. 10, ¶ [0042]-[0043]) wherein a bottom surface of an interlayer contact (600 including 1000) is lower than a top surface of a pad (107/109) with a distance (“d’), and wherein a width of a portion of the interlayer contact in a recessed portion (angled anchor 1000 is in a recess) of the pad (107/109) tapers downward (tapers to a triangular point as pictured).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the semiconductor device of Ma with an angled anchor between the interlayer contact (Ma 114 which becomes 118) and the landing pad (45) as taught by Wang in order to form an anchor which provides mechanical stability by holding each via securely in place with a lower metal line (Wang ¶ [0013]) and with a tapered profile as taught by Wang in order to prevent etchants from dispersing along grain boundaries and distorting the shape of the via anchor (Wang Abstract, ¶ [0014],[0043]).
Regarding claim 2, Ma in view of Wang yields the semiconductor device of claim 1, and Ma further discloses a dielectric layer (55, or 55 and 83 and 128 together, ¶ [0024]) covering the conductive layer (23) and the landing pad (45).
Regarding claim 3, Ma in view of Wang yields the semiconductor device of claim 2, and Ma further discloses wherein a top surface of the dielectric layer (top of 128) and a top surface of the interlayer contact (114/118) are coplanar (as pictured in FIG. 8).
Regarding claim 5, Ma in view of Wang yields the semiconductor device of claim 1, and Ma further discloses wherein a width of a bottom of the interlayer contact (118, from FIG. 6 width B) is less than (as pictured) a width of a top of the landing pad (45).
Regarding claim 6, Ma in view of Wang yields the semiconductor device of claim 5, and Ma further discloses wherein the width of the top of the interlayer contact (118) is greater than (as pictured) the width of the bottom of the interlayer contact (bottom of 118 with width B).
Regarding claim 7, Ma in view of Wang yields the semiconductor device of claim 1, and Ma further discloses wherein a width of a top of the landing pad (45) is greater than (as pictured) a width of a bottom of the landing pad (portion between interconnections 29).
Regarding claim 8, Ma in view of Wang yields the semiconductor device of claim 1, and Ma further discloses a contact material (lower portion of 45) filled in the trench and located below the landing pad (upper portion of 45).
Examiner’s Note: the language of contact material and landing pad are interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) to reasonably include instances wherein the contact material is the same material as the landing pad.
Regarding claim 9, Ma discloses a semiconductor device (FIG. 8), comprising:
a conductive layer (23, ¶ [0024],[0033]) having a trench (spaced between 29);
a landing pad (45, ¶ [0032],[0033]) filled in the trench;
a capacitor (138, ¶ [0053],[0054]) disposed over the landing pad; and
an interlayer contact (114 which becomes 118, ¶ [0046],[0047]) connected between the landing pad (45) and the capacitor (138), wherein a width of the interlayer contact (118) tapers downward (i.e. diminishes or reduces in thickness toward one end).
Ma fails to clearly teach wherein a bottom surface of the interlayer contact (114 which becomes 118) is lower than a top surface of the landing pad with a distance, and wherein the width of a portion of the interlayer contact in a recessed portion of the landing pad tapers downward.
Wang teaches (e.g. Fig. 10, ¶ [0042]-[0043]) wherein a bottom surface of an interlayer contact (600 including 1000) is lower than a top surface of a pad (107/109) with a distance (“d’), and wherein a width of a portion of the interlayer contact in a recessed portion (angled anchor 1000 is in a recess) of the pad (107/109) tapers downward (tapers to a triangular point as pictured).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the semiconductor device of Ma with an angled anchor between the interlayer contact (Ma 114 which becomes 118) and the landing pad (45) as taught by Wang in order to form an anchor which provides mechanical stability by holding each via securely in place with a lower metal line (Wang ¶ [0013]) and with a tapered profile as taught by Wang in order to prevent etchants from dispersing along grain boundaries and distorting the shape of the via anchor (Wang Abstract, ¶ [0014],[0043]).
Regarding claim 10, Ma in view of Wang yields the semiconductor device of claim 9, and Ma further discloses a dielectric layer (55, or 55 and 83 and 128 together, ¶ [0024]) covering the conductive layer (23) and the landing pad (45).
Regarding claim 11, Ma in view of Wang yields the semiconductor device of claim 10, and Ma further discloses wherein a top surface of the dielectric layer (top of 128) and a top surface of the interlayer contact (114/118) are coplanar (as pictured in FIG. 8).
Regarding claim 13, Ma in view of Wang yields the semiconductor device of claim 9, and Ma further discloses wherein a width of a top of the interlayer contact (118) is greater than a width of the capacitor (width of 132).
Regarding claim 15, Ma in view of Wang yields the semiconductor device of claim 9, and Ma further discloses wherein a width of a bottom of the interlayer contact (118, from FIG. 6 width B) is less than (as pictured) a width of a top of the landing pad (45).
Regarding claim 16, Ma in view of Wang yields the semiconductor device of claim 9, and Ma further discloses wherein a width of a top of the landing pad (45) is greater than a width of a bottom of the landing pad (portion of 45 between 29).
Regarding claim 17, Ma in view of Wang yields the semiconductor device of claim 9, and Ma further discloses a contact material (lower portion of 45) filled in the trench (space between 29) and located below the landing pad (upper portion of 45).
Examiner’s Note: the language of contact material and landing pad are interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) to reasonably include instances wherein the contact material is the same material as the landing pad.
Regarding claim 18, Ma discloses a method of manufacturing a semiconductor device (FIG. 8), comprising:
sequentially forming (FIG. 3) a conductive layer (23, ¶ [0024],[0033]), a contact material (lower portion of 45, ¶ [0032],[0033]), a landing pad (upper portion of 45), and (FIG. 4) a dielectric layer (55, ¶ [0024]), in which the contact material (lower 45) and the landing pad (upper 45) are filled in a trench of the conductive layer (spaced between 29) and the landing pad (upper portion of 45) overfills the trench, and in which the dielectric layer (55) covers the conductive layer (lower 45) and the landing pad (45);
forming (FIG. 6) a recess (portion 89 of width B, ¶ [0044]) on a top surface of the dielectric layer (55) to expose the landing pad (upper 45);
forming (FIG. 7) an interlayer contact (114, ¶ [0046],[0047]) filling the recess; and
forming (FIG. 8) a capacitor (138, ¶ [0053],[0054]) on the interlayer contact.
Ma fails to clearly teach wherein a bottom surface of the interlayer contact (114 which becomes 118) is lower than a top surface of the landing pad with a distance, and wherein the width of a portion of the interlayer contact in a recessed portion of the landing pad tapers downward.
Wang teaches (e.g. Fig. 10, ¶ [0042]-[0043]) wherein a bottom surface of an interlayer contact (600 including 1000) is lower than a top surface of a pad (107/109) with a distance (“d’), and wherein a width of a portion of the interlayer contact in a recessed portion (angled anchor 1000 is in a recess) of the pad (107/109) tapers downward (tapers to a triangular point as pictured).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the semiconductor device of Ma with an angled anchor between the interlayer contact (Ma 114 which becomes 118) and the landing pad (45) as taught by Wang in order to form an anchor which provides mechanical stability by holding each via securely in place with a lower metal line (Wang ¶ [0013]) and with a tapered profile as taught by Wang in order to prevent etchants from dispersing along grain boundaries and distorting the shape of the via anchor (Wang Abstract, ¶ [0014],[0043]).
Regarding claim 19, Ma in view of Wang yields the method of claim 18, and Wang further teaches (when applied to Ma) wherein forming the recess on the top surface of the dielectric layer (Wang Fig. 4 opening in dielectric 108/ILD2, Ma Fig. 5 opening A to Fig. 6 opening B) such that (Fig. 5) a portion (500) of the landing pad (when applied to Ma) is removed.
Regarding claim 20, Ma in view of Wang yields the method of claim 18, and Ma further discloses wherein forming a capacitor (138) on the interlayer contact (114) such that a width of the capacitor (width of 132) is less than a width of a top of the interlayer contact (top of 114).
Claims 9,13,14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2004/0238867 A1 to Park, “Park”, in view of US 2024/0079315 A1 to WANG et al., “Wang”.
Regarding claim 9, Park discloses a semiconductor device (FIG. 2), comprising:
a conductive layer (120, ¶ [0016]) having a trench (e.g. FIG. 4 trenches 134, ¶ [0023]);
a landing pad (144, ¶ [0024],[0025]) filled in the trench;
a capacitor (180a, ¶ [0016]) disposed over the landing pad; and
an interlayer contact (160a, ¶ [0032]) connected between the landing pad (144) and the capacitor (180a), wherein a width of the interlayer contact (160a) tapers downward (as pictured).
Park fails to clearly teach wherein a bottom surface of the interlayer contact (160a) is lower than a top surface of the landing pad with a distance, and wherein the width of a portion of the interlayer contact in a recessed portion of the landing pad tapers downward.
Wang teaches (e.g. Fig. 10, ¶ [0042]-[0043]) wherein a bottom surface of an interlayer contact (600 including 1000) is lower than a top surface of a pad (107/109) with a distance (“d’), and wherein a width of a portion of the interlayer contact in a recessed portion (angled anchor 1000 is in a recess) of the pad (107/109) tapers downward (tapers to a triangular point as pictured).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the semiconductor device of Park with an angled anchor between the interlayer contact and the landing pad (45) as taught by Wang in order to form an anchor which provides mechanical stability by holding each via securely in place with a lower metal line (Wang ¶ [0013]) and with a tapered profile as taught by Wang in order to prevent etchants from dispersing along grain boundaries and distorting the shape of the via anchor (Wang Abstract, ¶ [0014],[0043]).
Regarding claim 13, Park in view of Wang yields the semiconductor device of claim 9, and Park further discloses wherein a width of a top of the interlayer contact (top of 160a) is greater than a width of the capacitor (lower portion of 180a).
Regarding claim 14, Park in view of Wang yields the semiconductor device of claim 13, and Park further discloses wherein a width of a top of the landing pad (144) is less than (as pictured in FIG. 1 and FIG. 2) a width of the capacitor (180a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 8,644,766 B2 to Yang et al. teaches forming an opening (FIG. 5A) in an underlying conductive feature (20, column 9 lines 26-27) to form an anchoring area (32) wherein a width of a portion of the contact in a recessed portion tapers downward.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891
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