DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-19 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 14-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 14 recites “a dielectric layer disposed over the substrate; and a trench capacitor disposed on the channel structure, opposite to the substrate, wherein the trench capacitor comprises a first conductive layer and a second conductive layer and a first dielectric layer and a second dielectric layer…wherein the air gap structure comprises a liner layer is enclosed withing the second dielectric layer and an air gap enclosed within the liner layer”. Claim 14 as written is as if the air gap is in the second dielectric layer of the trench capacitor. Examiner notes that the air gap is not enclosed in the second dielectric layer of the trench capacitor. There is no support in the original disclosure for this recitation. Appropriate correction is required. Also, after inspection, the Examiner notes that claim 14 does not even belong to elected embodiment and sub-species. Applicant chose Species 1, Embodiment I, Fig. 1A and Sub-species B, Figs. 1A and 1D. Sub-species B does not include a trench capacitor with a first and second dielectric layer. Claims 14-19 belong to non-elected Sub-species C, Figs. 1A, 1E, which include a trench capacitor with a first and second dielectric layer. “[0077] The multilayered stack of the trench capacitor 160 in FIG. 1B includes two conductive layers 161 and 163 and one dielectric layer 162. However, in alternative embodiments, the multilayered stack of the trench capacitor 160 may include more conductive layers and more dielectric layers. For example, the trench capacitor 160 may include two conductive layers 161 and 163 and two dielectric layers 162 and 165, in accordance with FIG. 1E”. For the purpose of examination, the Examiner will take the recitation to be ““a dielectric layer disposed over the substrate; and a trench capacitor disposed on the channel structure, opposite to the substrate, wherein the trench capacitor comprises a first conductive layer and a second conductive layer and a/a first dielectric layer…wherein the air gap structure comprises a liner layer is enclosed within a second dielectric layer and an air gap enclosed within the liner layer” so that they read on the elected embodiment and species. Claims 15-19 inherit these deficiencies due to their dependency.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 14 recites “a dielectric layer disposed over the substrate; and a trench capacitor disposed on the channel structure, opposite to the substrate, wherein the trench capacitor comprises a first conductive layer and a second conductive layer and a first dielectric layer and a second dielectric layer…wherein the air gap structure comprises a liner layer is enclosed within the second dielectric layer and an air gap enclosed within the liner layer”. Examiner notes that the air gap is not enclosed in the second dielectric layer of the trench capacitor. Paragraph [0073] of the Applicant’s specification recites “the trench capacitors 160 may include a multilayered stack (including conductive layers 161 and 163 and a dielectric layer 162) and a contact material 164”. After inspection, the Examiner notes that claim 14 does not even belong to elected embodiment or sub-species. Applicant chose Species 1, Embodiment I, Fig. 1A and Sub-species B, Figs. 1A and 1D. Sub-species B does not include a trench capacitor with a first and second dielectric layer. Claims 14-19 belong to non-elected Sub-species C, Figs. 1A, 1E, which include a trench capacitor with a first and second dielectric layer. “[0077] The multilayered stack of the trench capacitor 160 in FIG. 1B includes two conductive layers 161 and 163 and one dielectric layer 162. However, in alternative embodiments, the multilayered stack of the trench capacitor 160 may include more conductive layers and more dielectric layers. For example, the trench capacitor 160 may include two conductive layers 161 and 163 and two dielectric layers 162 and 165, in accordance with FIG. 1E”. Claims 14-19 should be withdrawn or amended to read on the elected embodiment and sub-species. For the purpose of examination, the Examiner will take the recitation to be “a dielectric layer disposed over the substrate; and a trench capacitor disposed on the channel structure, opposite to the substrate, wherein the trench capacitor comprises a first conductive layer and a second conductive layer and a/a first dielectric layer…wherein the air gap structure comprises a liner layer is enclosed within a second dielectric layer and an air gap enclosed within the liner layer” so that claim 14 reads on the elected embodiment and sub-species Claims 15-19 inherit these deficiencies due to their dependency. Appropriate correction is required. Examiner suggest that the Applicant make sure all claims read on the elected embodiment.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2021/0104525 A1) as evidenced by or in view of Liu et al. (Liu) (US 2023/0380136 A1).
In regards to claim 1, Tsai (Figs. 1, 2 and associated text) discloses a semiconductor device (item 1000), comprising: a substrate (item 10); a first bit line (items BL1, BL2 or BL3) disposed on the substrate (item 10) and extending along a first direction (D2); a first word line (item WL1, WL2 or WL3) disposed on the first bit line (items BL1, BL2 or BL3) and extending along a second direction (z-direction[D3] or D1) perpendicular to the first direction (D2); a channel structure (items 120, 220) disposed on the first bit line (items BL1, BL2 or BL3) and penetrating the first word line (item WL1, WL2 or WL3), wherein the channel structure (items 120, 220) is separated from the first word line (item WL1, WL2 or WL3) by a gate dielectric layer (item 122); a first dielectric layer (item 30) disposed over the first bit line (items BL1, BL2 or BL3) and a second dielectric layer (items 12, 20 or 12 plus 20) disposed over the first word line (item WL1, WL2 or WL3), wherein the second dielectric layer (items 12, 20 or 12 plus 20) comprises a first air gap structure (item AG, paragraphs 6, 15, 35, 41, 55, claims 4, 13, ); and a trench capacitor (item 100C) disposed on the channel structure (items 120, 220), but does not specifically disclose wherein the first air gap structure is enclosed within the second dielectric layer.
Liu (paragraph 69, 73, 77, Fig. 4C and associated text) discloses a first dielectric layer (first plurality of ILD layers of item 4022, paragraph 69), a second dielectric (second plurality of ILD layers where item 402, 4028 and 4046 reside, paragraphs 73, 77) disposed over the first word line (item 4034), wherein the first air gap structure (air gap shown but not labeled) can be enclosed within the second dielectric layer (second plurality of ILD layers where item 402, 4028 and 4046 reside, paragraph 77).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Liu for the purpose of improving insulation (paragraph 77).
In regards to claim 12, Tsai (Figs. 1, 2 and associated text) as modified by Liu (paragraph 69, 73, 77, Fig. 4C and associated text) discloses wherein the first air gap structure (item AG) of the second dielectric layer (item 12) comprises an air gap (item AG) enclosed by a liner layer (item 20), wherein the liner layer (item 20, Tsai) is enclosed withing the second dielectric layer (item 12, Tsai, second plurality of ILD layers where item 402, 4028 and 4046 reside, paragraph 77, Liu) and is spaced apart from the channel structure (items 120, 220, Tsai, item 4030, paragraph 72, Liu).
In regards to claim 13, Tsai (Figs. 1, 2 and associated text) as modified by Liu (paragraph 69, 73, 77, Fig. 4C and associated text) discloses wherein the first air gap structure (item AG, Tsai, shown but not labeled, Liu) is formed by a thermal treatment process that/and the first gap structure (item AG, Tsai, shown but not labeled, Liu) is formed between a top surface and a bottom surface of the second dielectric layer (item 12, Tsai, second plurality of ILD layers where item 402, 4028 and 4046 reside, paragraph 77, Liu). Examiner notes that “the first air gap structure is formed by a thermal treatment process” is a “product-by-process” limitation.
"Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F. 2d 695, 698, 227 USPQ 964, 966 (fed Cir. 1985).
The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, this limitation, “formed by a thermal treatment process”, has not been given patentable weight.
Claim(s) 1-3, 5, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon) (US 2023/0061185 A1) in view of Tsai (US 2021/0104525 A1) as evidenced by or in view of Liu et al. (Liu) (US 2023/0380136 A1).
In regards to claim 1, Jeon (Figs. 10-12 and associated text) In regards to claim 1, discloses a semiconductor device (Fig. 12), comprising: a substrate (item 200); a first bit line (item 420) disposed on the substrate (item 200) and extending along a first direction (y-direction); a first word line (item 440) disposed on the first bit line (item 420) and extending along a second direction (x-direction) perpendicular to the first direction (y-direction); a channel structure (item 430) disposed on the first bit line (item 420) and penetrating the first word line (item 440), wherein the channel structure (item 430) is separated from the first word line (item 440) by a gate dielectric layer (item 450); a first dielectric layer (item 422) disposed over the first bit line (item 420) and a second dielectric layer (item 436) disposed over the first word line (item 440), and a trench capacitor (item 480) disposed on the channel structure (item 430), but does not specifically disclose wherein the second dielectric layer comprises a first air gap structure.
In regards to claim 1, Tsai (Figs. 1, 2 and associated text) discloses wherein the second dielectric layer (items 12, 20 or 12 plus 20) comprises a first air gap structure (item AG, paragraphs 6, 15, 35, 41, 55, claims 4, 13, ).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings Tsai for the purpose of reducing parasitic capacitance (paragraph 60).
Jeon as modified by Tsai does not specifically disclose wherein the first air gap structure is enclosed within the second dielectric layer.
Liu (paragraph 69, 73, 77, Fig. 4C and associated text) discloses a first dielectric layer (first plurality of ILD layers of item 4022, paragraph 69), a second dielectric (second plurality of ILD layers where item 402, 4028 and 4046 reside, paragraphs 73, 77) disposed over the first word line (item 4034), wherein the first air gap structure (air gap shown but not labeled) can be enclosed within the second dielectric layer (second plurality of ILD layers where item 402, 4028 and 4046 reside, paragraph 77).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Liu for the purpose of improving insulation (paragraph 77).
In regards to claim 2, Jeon (Figs. 10-12 and associated text) as modified by Tsai and Liu does not specifically disclose further comprising a first landing pad (LP) disposed between the channel structure and the first bit line.
However, in another embodiment of Jeon (paragraphs 45-50) discloses comprising a first landing pad (LP) (item LP) disposed between the channel structure and the first bit line.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings from other embodiments of Jeon for the purpose of increasing the contact area via the introduction of the landing pad LP which may allow a contact resistance between the active area ACT and the lower electrode of the capacitor to be reduced (paragraph 48).
In regards to claim 3, Jeon as modified by Tsai and Liu does not specifically disclose wherein the first landing pad contacts the first bit line through a titanium nitride layer.
However, Jeon teaches the first bit line (420) may include at least one of polysilicon doped with impurities, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAIN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but may not be limited thereto. Each of the plurality of first bit line conductive films may include a single layer or multiple layers made of the aforementioned materials (paragraph 159).
In another embodiment, Jeon teaches further comprising a first landing pad (LP) disposed between the channel structure and the first bit line (paragraphs 45-50) and thus Jeon makes it obvious wherein the first landing pad contacts the first bit line through a titanium nitride layer.
It would have been obvious to one of ordinary skill in the art before the effective
filing date of the claimed invention to combine the teachings of Jeon so that wherein the first landing pad contacts the first bit line through a titanium nitride layer, there is improved performance and reliability (paragraph 5).
In regards to claim 5, Jeon (Figs. 10-12 and associated text) does not specifically disclose further comprising a second landing pad (LP) (item LP) disposed between the trench capacitor and the channel structure
However, in another embodiment of Jeong (paragraphs 45-50) discloses comprising a first landing pad (LP) (item LP) disposed between the trench capacitor and the channel structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings from other embodiments of Jeon for the purpose of increasing the contact area via the introduction of the landing pad LP which may allow a contact resistance between the active area ACT and the lower electrode of the capacitor to be reduced (paragraph 48).
Therefore Jeon (Figs. 10-12 and associated text) as modified by Tsai (Figs. 1, 2 and associated text) and Liu (paragraph 69, 73, 77, Fig. 4C and associated text) discloses further comprising a second landing pad (LP) (item LP) disposed between the trench capacitor (item 480) and the channel structure (item 430); wherein the second landing pad (item LP) is surrounded by the second dielectric layer (items 12, 20 or 12 plus 20, Tsai, second plurality of ILD layers where item 402, 4028 and 4046 reside, paragraph 77, Liu) and is spaced apart from the first air gap structure (item AG, Tsai, shown but not labeled, Liu).
In regards to claim 12, Jeon as modified by Tsai (Figs. 1, 2 and associated text) and Liu (paragraph 69, 73, 77, Fig. 4C and associated text) discloses wherein the first air gap structure (item AG) of the second dielectric layer (item 12) comprises an air gap (item AG) enclosed by a liner layer (item 20), wherein the liner layer (item 20, Tsai) is enclosed withing the second dielectric layer (item 12, Tsai, second plurality of ILD layers where item 402, 4028 and 4046 reside, paragraph 77, Liu) and is spaced apart from the channel structure (items 120, 220, Tsai, item 4030, paragraph 72, Liu).
In regards to claim 13, Jeon as modified by Tsai (Figs. 1, 2 and associated text) and Liu (paragraph 69, 73, 77, Fig. 4C and associated text) discloses wherein the first air gap structure (item AG, Tsai, shown but not labeled, Liu) is formed by a thermal treatment process that/and the first gap structure (item AG, Tsai, shown but not labeled, Liu) is formed between a top surface and a bottom surface of the second dielectric layer (item 12, Tsai, second plurality of ILD layers where item 402, 4028 and 4046 reside, paragraph 77, Liu). Examiner notes that “the first air gap structure is formed by a thermal treatment process” is a “product-by-process” limitation.
"Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F. 2d 695, 698, 227 USPQ 964, 966 (fed Cir. 1985).
The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, this limitation, “formed by a thermal treatment process”, has not been given patentable weight.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon) (US 2023/0061185 A1) in view of Tsai (US 2021/0104525 A1) as evidenced by or in view of Liu et al. (Liu) (US 2023/0380136 A1) as applied to claims 1-3 and 5 above, and further in view of Ryu et al. (Ryu) (US 2022/0223732 A1).
In regards to claim 4, Jeon as modified by Tsai and Liu does not specifically disclose further comprising an indium tin oxide (ITO) layer disposed between the channel structure and the first landing pad.
Ryu (paragraphs 92, 93) discloses further comprising an indium tin oxide (ITO) layer disposed between the channel structure and the first landing pad.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Ryu for the purpose improved performance by improving interface characteristics while reducing leakage current (paragraph 5).
Claim(s) 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (Jeon) (US 2023/0061185 A1) in view of Tsai (US 2021/0104525 A1) as evidenced by or in view of Liu et al. (Liu) (US 2023/0380136 A1) as applied to claims 1-3 and 5 above, and further in view of Cho et al. (US 2022/0013525 A1).
In regards to claim 6, Jeon as modified by Tsai and Liu does not specifically disclose further comprising: a first conductive layer disposed between the substrate and the first bit line; and a first contact disposed on and electrically connected to the first conductive layer, wherein the first contact is spaced apart from the channel structure.
Cho (Fig. 26 and associated text) discloses further comprising: a first conductive layer (item 414) disposed between the substrate (item 100) and the first bit line (item 210); and a first contact (item 412) disposed on and electrically connected to the first conductive layer (item 414), wherein the first contact (item 412) is spaced apart from the channel structure (item 310).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Cho for the purpose of an electrical connection.
In regards to claim 7, Cho (Fig. 26 and associated text) discloses wherein the first contact (item 412) is a monolithic structure.
In regards to claim 8, Jeon as modified by Tsai, Liu and Cho (Fig. 26 and associated text) discloses further comprising a second contact (another item 412) disposed between the first word line (item 220) and the first conductive layer (item 414), wherein the second contact (another item 412) is spaced apart from the channel structure (item 310).
In regard to claim 9, Jeon (Figs. 10-12 and associated text) discloses further comprising: a polysilicon layer (item 460, paragraph 165) disposed on the trench capacitor (item 480) opposite to the channel structure, further comprising a polysilicon layer (item 460) disposed on the trench capacitor (item 480), opposite to the channel structure, wherein the polysilicon layer (item 460) has a first sidewall.
In regard to claim 10, Jeon (Figs. 10-12 and associated text) discloses wherein the first sidewall is non-planar.
In regard to claim 11, Jeon (Figs. 10-12 and associated text) discloses further comprising a second conductive layer (items 483 or 485) disposed on the polysilicon layer (item 460), wherein the second conductive layer (items 483 or 485) has a second sidewall, and wherein the first sidewall is recessed from the second sidewall of the second conductive layer (items 483 or 485).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 September 3, 2026
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