DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 4, and 6 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,823,359 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1-2, 4, and 6 are anticipated by claims 1-20 of the patent, and it is not patentably distinct from claims 1-20 of the patent. See the Table as shown below:
Claims of Application under examination
Patented Claims
1. A fin field effect transistor (FinFET) device structure, comprising:
a first fin structure extending above a substrate;
a first liner layer formed on a first sidewall surface of the first fin structure; and
a gate dielectric layer formed over the first fin structure and the first liner layer, wherein a sidewall surface of the gate dielectric layer is aligned with a sidewall surface of the first liner layer.
Anticipated by patented claim 7:
7. A fin field effect transistor (FinFET) device structure, comprising:
a first fin structure extending above a substrate;
a second fin structure adjacent to the first fin structure, wherein the first fin structure comprises an inner sidewall surface close to the second fin structure and an outer sidewall surface away from the second fin structure;
a first liner layer formed on the inner sidewall surface of the first fin structure;
a second liner layer formed on the outer sidewall surface of the first fin structure, wherein a top surface of the first liner layer is higher than a top surface of the second liner layer;
a third fin structure formed adjacent to the second fin structure;
a first gate electrode formed over the first fin structure and the second fin structure; a second gate electrode formed over the third fin structure, wherein the first gate electrode is separated from the second gate electrode; and
a first gate dielectric layer between the first gate electrode and the first fin structure,
wherein a sidewall surface of the first gate dielectric layer is aligned with a sidewall surface of the first liner layer.
2. The fin field effect transistor (FinFET) device structure as claimed in claim 1, further comprising:
a second fin structure adjacent to the first fin structure, wherein the first liner layer extends to a sidewall surface of the second fin structure, wherein the first liner layer has a U-shaped structure.
Anticipated by patented claims 9 and 17:
9. The fin field effect transistor (FinFET) device structure as claimed in claim 7, wherein the first liner layer extends from the inner sidewall surface of the first fin structure to an inner sidewall surface of the second fin structure (as patented in patented claim 9); and
17. The fin field effect transistor (FinFET) device structure as claimed in claim 7, wherein the first liner layer has a U-shaped structure (as patented in claim 17).
4. The fin field effect transistor (FinFET) device structure as claimed in claim 1, further comprising:
an isolation structure formed on the substrate, wherein the isolation structure has a recessed top surface.
Anticipated by patented claim 19.
19. The fin field effect transistor (FinFET) device structure as claimed in claim 18, further comprising: an isolation structure adjacent to the first liner layer, wherein the isolation structure has a curved top surface.
Note: the patented “curved top surface” is equivalent to the claimed limitation of “recessed top surface”
6. The fin field effect transistor (FinFET) device structure as claimed in claim 1, further comprising:
a second liner layer formed on a second sidewall surface of the first fin structure, wherein a topmost surface of the first liner layer is higher than a topmost surface of the second liner layer.
Anticipated by patented claim 7.
7. A fin field effect transistor (FinFET) device structure, comprising:
a first fin structure extending above a substrate;
a second fin structure adjacent to the first fin structure, wherein the first fin structure comprises an inner sidewall surface close to the second fin structure and an outer sidewall surface away from the second fin structure;
a first liner layer formed on the inner sidewall surface of the first fin structure;
a second liner layer formed on the outer sidewall surface of the first fin structure, wherein a top surface of the first liner layer is higher than a top surface of the second liner layer;
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-7, 9-10, and 16 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim et al. (U.S. 2017/0125597 A1, hereinafter refer to Kim).
Regarding Claim 1: Kim discloses a fin field effect transistor (FinFET) device structure (see Figs.6A-6B and 8-9 as shown below and ¶ [0007]), comprising:
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a first fin structure (F2) extending above a substrate (100) (see Kim, Fig.8 as shown above);
a first liner layer (L2) formed on a first sidewall surface of the first fin structure (F2) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]); and
a gate dielectric layer (130/140) formed over the first fin structure (F2) and the first liner layer (L2), wherein a sidewall surface of the gate dielectric layer (130/140) is aligned with a sidewall surface of the first liner layer (L2) (note: Kim is silent to demonstrate the arrangements of gate dielectric layer with relative to liner layer. Kim demonstrate the arrangements of gate dielectric layer with relative to field isolation film which teaches the sidewall surface of the gate dielectric layer (130/140) is aligned with a sidewall surface of the first filed isolation film (ST2/110). Since, the first liner layer (L2) formed on a first sidewall surface of the first fin structure and protruding above the top surface of filed isolation film 110 as demonstrated in Fig.6 as shown above, ordinary skill in the art recognize that the Kim sidewall surface of the gate dielectric layer necessarily aligned with a sidewall surface of the first liner layer as specified now in claim 1. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein a sidewall surface of the gate dielectric layer (124) is aligned with a sidewall surface of the first liner layer (132)) (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 2: Kim discloses a fin field effect transistor (FinFET) device structure as set forth in claim 1 as above. Kim further teaches a second fin structure (F1) adjacent to the first fin structure (F2), wherein the first liner layer (L2) extends to a sidewall surface of the second fin structure (F1), wherein the first liner layer (L2) has a U-shaped structure (note: since, the STI structure has a U-shaped structure, the first liner layer L2 necessarily have a U-shaped structure. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein the first liner layer (132) has a U-shaped structure) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]).
Regarding Claim 4: Kim discloses a fin field effect transistor (FinFET) device structure as set forth in claim 1 as above. Kim further teaches wherein an isolation structure (110) formed on the substrate (100), wherein the isolation structure (110) has a recessed top surface (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 5: Kim discloses a fin field effect transistor (FinFET) device structure as set forth in claim 4 as above. Kim further teaches wherein the isolation structure (110) is surrounded by the first liner layer (L2) and the gate dielectric layer (130/140) (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 6: Kim discloses a fin field effect transistor (FinFET) device structure as set forth in claim 1 as above. Kim further teaches wherein a second liner layer (L2) formed on a second sidewall surface of the first fin structure (F2), wherein a topmost surface of the first liner layer is higher than a topmost surface of the second liner layer (L2) (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 7: Kim discloses a fin field effect transistor (FinFET) device structure as set forth in claim 6 as above. Kim further teaches wherein a width of the second liner layer (L2 within isolation 120) is greater than a width of the first liner layer (L1 within isolation 110) (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 9: Kim discloses a fin field effect transistor (FinFET) device structure (see Figs.6A-6B and 8-9 as shown above and ¶ [0007]), comprising:
a first fin structure (F2) extending above a substrate (100) (see Kim, Figs.6 and 8 as shown above);
a second fin structure (F1) adjacent to the first fin structure (F2), wherein the first fin structure (F2) comprises an inner sidewall surface close to the second fin structure (F1) and an outer sidewall surface away from the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above);
a first liner layer (L2) formed on the inner sidewall surface of the first fin structure (F2) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]);
a second liner layer (L2) formed on the outer sidewall surface of the first fin structure (F2) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]);
a first isolation structure (110) surrounded by the first liner layer (L2) (see Kim, Figs.6 and 8 as shown above); and
a second isolation structure (120) surrounded by the second liner layer (L2), wherein a width of the second isolation structure (120) is greater than a width of the first isolation structure (110) (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 10: Kim discloses a fin field effect transistor (FinFET) device structure as set forth in claim 9 as above. Kim further teaches wherein a height of the second isolation structure (120) is smaller than a height of the first isolation structure (110) (see Kim, Fig.8 as shown above).
Regarding Claim 16: Kim discloses a fin field effect transistor (FinFET) device structure (see Figs.6A-6B and 8-9 as shown above and ¶ [0007]), comprising:
a first fin structure (F2) extending above a substrate (100) (see Kim, Figs.6 and 8 as shown above);
a second fin structure (F1) adjacent to the first fin structure (F2), wherein the first fin structure (F2) comprises an inner sidewall surface close to the second fin structure (F1) and an outer sidewall surface away from the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above);
a first U-shaped liner layer (L2) formed on the inner sidewall surface of the first fin structure (F2) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (note: since, the STI structure has a U-shaped structure, the first liner layer L2 necessarily have a U-shaped structure. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein the first liner layer (132) has a U-shaped structure) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]); and
a second U-shaped liner layer (L2) formed on the outer sidewall surface of the first fin structure (F2), wherein a width of the second U-shaped liner layer (L2, at ST3 or ST1 region) is greater than a width of the first U-shaped liner layer (L2, at ST2 region) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (note: since, the STI structure has a U-shaped structure, the first liner layer L2 necessarily have a U-shaped structure. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein the first liner layer (132) has a U-shaped structure) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2017/0125597 A1, hereinafter refer to Kim).
Regarding Claim 17: Kim discloses a fin field effect transistor (FinFET) device structure as set forth in claim 16 as above. Kim further teaches wherein a first isolation structure (110) surrounded by the first U-shaped liner layer (L2) (see Kim, Figs.6 and 8 as shown above);
a second isolation structure (120) surrounded by the second U-shaped liner layer (L2) (see Kim, Figs.6 and 8 as shown above); and
a gate dielectric layer (130/140) formed on the first isolation structure (110) and the second isolation structure (120) (see Kim, Figs.6 and 8 as shown above).
First embodiment Fig.8 of Kim is silent upon explicitly disclosing wherein a portion of the second isolation structure is not covered by the gate dielectric layer.
Second embodiment of Kim teaches wherein a portion of the second isolation structure (120/150) is not covered by the gate dielectric layer (130/141/142) (see Kim, Figs.12-13).
Hence, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of first and second embodiment of Kim to enable portion of the second isolation structure is not covered by the gate dielectric layer in order to ensure spacing margin has to be ensured between the first gate electrode and the second gate electrode.
Claim(s) 3, 11-15, and 18- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2017/0125597 A1, hereinafter refer to Kim) as applied to claims 2, 10, and 16 above, and further in view of Kim et al. (U.S. 2016/0315193 A1, hereinafter refer to Kim’193).
Regarding Claim 3: Kim discloses a fin field effect transistor (FinFET) device structure as applied to claim 2 above. Kim further teaches wherein a third fin structure (F3) adjacent to the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above).
Kim is silent upon explicitly disclosing wherein a fourth fin structure adjacent to the third fin structure, wherein a distance between the third fin structure and the fourth fin structure is greater than a distance between the first fin structure and the second fin structure.
For support see Kim’193, which teaches wherein a fourth fin structure (F4) adjacent to the third fin structure (F3), wherein a distance between the third fin structure (F3) and the fourth fin structure (F4) is greater than a distance between the first fin structure (F1) and the second fin structure (F2) (see Kim’193, Fig.6 as shown below and ¶ [0038]) .
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Kim’193 to enable the Kim fin structure to include a fourth fin structure adjacent to the third fin structure, wherein a distance between the third fin structure and the fourth fin structure to be greater than a distance between the first fin structure and the second fin structure as taught by Kim’193 in order to improve the electrical characteristic of the fin structure.
Regarding Claim 11: Kim discloses a fin field effect transistor (FinFET) device structure as applied to claim 10 above. Kim is silent upon explicitly disclosing wherein the first fin structure has a bottom portion and a top portion, the bottom portion and the top portion of the first fin structure are made of different materials, and a first interface is between the top portion and the bottom portion.
For support see Kim’193, which teaches wherein the first fin structure (F1) has a bottom portion and a top portion, the bottom portion (102f) and the top portion (103f) of the first fin structure (F1) are made of different materials, and a first interface is between the top portion (103f) and the bottom portion (102f) (see Kim’193, Fig.6 as shown above and ¶ [0037]- ¶ [0038]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Kim’193 to enable the Kim’s fin structure to include a bottom portion and a top portion, the bottom portion and the top portion of the first fin structure to be made of different materials, and a first interface between the top portion and the bottom portion as taught by Kim’193 in order to improve the electrical characteristic of the fin structure.
Regarding Claim 12: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 11 as above. The combination of Kim and Kim’193 further teaches wherein the first interface is higher than a top surface of the second isolation structure (isolation region between F1 and F3) (see Kim’193, Fig.6 as shown above).
Regarding Claim 13: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 11 as above. The combination of Kim and Kim’193 further teaches wherein a top surface of the first isolation structure (isolation region between F1 and F2) is closer to the first interface than the second isolation structure (isolation region between F1 and F3) (see Kim’193, Fig.6 as shown above).
Regarding Claim 14: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 11 as above. The combination of Kim and Kim’193 further teaches wherein a gate dielectric layer (320) formed over the first fin structure, wherein a portion of the gate dielectric layer (320) is lower than the first interface (see Kim’193, Fig.6 as shown above and Fig.2C).
Regarding Claim 15: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 14 as above. The combination of Kim and Kim’193 further teaches wherein a sidewall surface of the gate dielectric layer (130/140) is aligned with a sidewall surface of the first liner layer (L2) (note: Kim is silent to demonstrate the arrangements of gate dielectric layer with relative to liner layer. Kim demonstrate the arrangements of gate dielectric layer with relative to field isolation film which teaches the sidewall surface of the gate dielectric layer (130/140) is aligned with a sidewall surface of the first filed isolation film (ST2/110). Since, the first liner layer (L2) formed on a first sidewall surface of the first fin structure and protruding above the top surface of filed isolation film 110 as demonstrated in Fig.6 as shown above, ordinary skill in the art recognize that the Kim sidewall surface of the gate dielectric layer necessarily aligned with a sidewall surface of the first liner layer as specified now in claim 1. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein a sidewall surface of the gate dielectric layer (124) is aligned with a sidewall surface of the first liner layer (132)) (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 18: Kim discloses a fin field effect transistor (FinFET) device structure as applied to claim 16 above. Kim is silent upon explicitly disclosing wherein the first fin structure has a bottom portion and a top portion, the bottom portion and the top portion of the first fin structure are made of different materials, and a first interface is between the top portion and the bottom portion.
For support see Kim’193, which teaches wherein the first fin structure (F1) has a bottom portion and a top portion, the bottom portion (102f) and the top portion (103f) of the first fin structure (F1) are made of different materials, and a first interface is between the top portion (103f) and the bottom portion (102f) (see Kim’193, Fig.6 as shown above and ¶ [0037]- ¶ [0038]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Kim’193 to enable the Kim’s fin structure to include a bottom portion and a top portion, the bottom portion and the top portion of the first fin structure to be made of different materials, and a first interface between the top portion and the bottom portion as taught by Kim’193 in order to improve the electrical characteristic of the fin structure.
Regarding Claim 19: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 18 as above. The combination of Kim and Kim’193 is silent upon explicitly disclosing wherein the first liner layer is closer to the first interface than the second liner layer.
However, practicing the combination of Kim and Kim’193 to modify the Kim’s fin structure to include a bottom portion and a top portion, the bottom portion and the top portion of the first fin structure to be made of different materials, and a first interface between the top portion and the bottom portion and the first isolation structure to be closer to the first interface than the second isolation structure according to the teachings of Kim’s’193 necessarily results the claimed limitation of “the first liner layer is closer to the first interface than the second liner layer” as now specified in claim 19.
Regarding Claim 20: Kim discloses a fin field effect transistor (FinFET) device structure as applied to claim 16 above. Kim further teaches wherein a third fin structure (F3) adjacent to the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above);
a third U-shaped liner layer (L2) formed between the fins structure (see Kim, Figs.6 and 8 as shown above).
Kim is silent upon explicitly disclosing wherein a fourth fin structure adjacent to the third fin structure.
For support see Kim’193, which teaches wherein a third fin structure (F3) adjacent to the second fin structure (F2) (see Kim’193, Fig.6 as shown above and ¶ [0038]);
a fourth fin structure (F4) adjacent to the third fin structure (F3) (see Kim’193, Fig.6 as shown above and ¶ [0038]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Kim’193 to enable the Kim fin structure to include a fourth fin structure adjacent to the third fin structure, wherein a distance between the third fin structure and the fourth fin structure to be greater than a distance between the first fin structure and the second fin structure as taught by Kim’193 in order to improve the electrical characteristic of the fin structure.
The combination of Kim and Kim’193 is silent upon explicitly disclosing wherein a third U-shaped liner layer formed between the third fin structure and the fourth fin structure, wherein a width of the third U-shaped liner layer is greater than the width of the first U-shaped liner layer and smaller than the width of the second U-shaped liner layer.
However, practicing the combination of Kim and Kim’193 to modify the Kim’s fin structure to include a fourth fin structure adjacent to the third fin structure, wherein a distance between the third fin structure and the fourth fin structure to be greater than a distance between the first fin structure and the second fin structure according to the teachings of Kim’s ‘193 necessarily results the claimed limitation of “a third U-shaped liner layer formed between the third fin structure and the fourth fin structure, wherein a width of the third U-shaped liner layer is greater than the width of the first U-shaped liner layer and smaller than the width of the second U-shaped liner layer” as now specified in claim 20.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2017/0125597 A1, hereinafter refer to Kim) as applied to claim 1 above, and further in view of Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung).
Regarding Claim 8: Kim discloses a fin field effect transistor (FinFET) device structure as applied to claim 1 above. Kim further teaches wherein a gate electrode layer (200) formed on the gate dielectric layer (130/140) (see Kim, Figs.6 and 8 as shown above).
Kim is silent upon explicitly disclosing wherein a portion of the gate electrode layer is lower than a top surface of the first liner layer.
For support see Sung, which teaches wherein a portion of the gate electrode layer (150) is lower than a top surface of the first liner layer (132) (see Sung, Fig.2 as shown below and ¶ [0004]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Sung to enable the Kim portion of the gate electrode layer to be lower than a top surface of the first liner layer as taught by Sung in order to improve the performance of a highly integrated fin field effect transistor (FET).
Conclusion
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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