Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2017/0125597 A1, hereinafter refer to Kim) in view of Sung et al. (U.S. 2016/0071932 A1, hereinafter refer to Sung).
Regarding Claim 1: Kim discloses a fin field effect transistor (FinFET) device structure (see Figs.6A-6B and 8-9 as shown below and ¶ [0007]), comprising:
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a first fin structure (F2) extending above a substrate (100), wherein the first fin structure (F2) comprises a bottom portion (F2L/F2U1) and a top portion (F2U2), and an interface (S2) is between the top portion (F2U2) and the bottom portion (F2L/F2U1) (see Kim, Figs.6 and 8 as shown above and ¶ [0082]);
a first liner layer (L2) formed on a first sidewall surface of the first fin structure (F2) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]); and
a gate dielectric layer (130/140) formed over the first fin structure (F2) and the first liner layer (L2), wherein a sidewall surface of the gate dielectric layer (130/140) is aligned with a sidewall surface of the first liner layer (L2) (note: Kim is silent to demonstrate the arrangements of gate dielectric layer with relative to liner layer. Kim demonstrates the arrangements of gate dielectric layer with relative to field isolation film which teaches the sidewall surface of the gate dielectric layer (130/140) is aligned with a sidewall surface of the first filed isolation film (ST2/110). Since, the first liner layer (L2) formed on a first sidewall surface of the first fin structure and protruding above the top surface of filed isolation film 110 as demonstrated in Fig.6 as shown above, ordinary skill in the art recognize that the Kim sidewall surface of the gate dielectric layer necessarily aligned with a sidewall surface of the first liner layer as specified now in claim 1. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein a sidewall surface of the gate dielectric layer (124) is aligned with a sidewall surface of the first liner layer (132)) (see Kim, Figs.6 and 8 as shown above).
Kim is silent upon explicitly disclosing wherein a slope of the bottom portion is the same as a slope of the top portion.
For support see Sung, which teaches wherein a slope of the bottom portion (411) is the same as a slope of the top portion (415b) (see Sung, Fig.4G as shown below, abstract, and ¶ [0016]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Sung to enable the Sung’s first fin structure to comprises a bottom portion and a top portion, and an interface to be between the top portion and the bottom portion, and a slope of the bottom portion is the same as a slope of the top portion as taught by Sung in order to obtain the FinFET structures have a uniform channel size defined only by upper fin portions thereof.
Regarding Claim 2: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 1 as above. The combination of Kim and Sung further teaches a second fin structure (F1) adjacent to the first fin structure (F2), wherein the first liner layer (L2) extends to a sidewall surface of the second fin structure (F1), wherein the first liner layer (L2) has a U-shaped structure (note: since, the STI structure has a U-shaped structure, the first liner layer L2 necessarily have a U-shaped structure. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein the first liner layer (132) has a U-shaped structure) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]).
Regarding Claim 4: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 1 as above. The combination of Kim and Sung further teaches wherein an isolation structure (110) formed on the substrate (100), wherein the isolation structure (110) has a recessed top surface (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 5: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 4 as above. The combination of Kim and Sung further teaches wherein the isolation structure (110) is surrounded by the first liner layer (L2) and the gate dielectric layer (130/140) (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 6: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 1 as above. The combination of Kim and Sung further teaches wherein a second liner layer (L2) formed on a second sidewall surface of the first fin structure (F2), wherein a topmost surface of the first liner layer is higher than a topmost surface of the second liner layer (L2) (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 7: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 6 as above. The combination of Kim and Sung further teaches wherein a width of the second liner layer (L2 within isolation 120) is greater than a width of the first liner layer (L1 within isolation 110) (see Kim, Figs.6 and 8 as shown above).
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2017/0125597 A1, hereinafter refer to Kim) and Sung et al. (U.S. 2016/0071932 A1, hereinafter refer to Sung) as applied to claim 2 above, and further in view of Kim et al. (U.S. 2016/0315193 A1, hereinafter refer to Kim’193).
Regarding Claim 3: Kim as modified teaches a fin field effect transistor (FinFET) device structure as applied to claim 2 above. The combination of Kim and Sung further teaches wherein a third fin structure (F3) adjacent to the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above).
The combination of Kim and Sung is silent upon explicitly disclosing wherein a fourth fin structure adjacent to the third fin structure, wherein a distance between the third fin structure and the fourth fin structure is greater than a distance between the first fin structure and the second fin structure.
For support see Kim’193, which teaches wherein a fourth fin structure (F4) adjacent to the third fin structure (F3), wherein a distance between the third fin structure (F3) and the fourth fin structure (F4) is greater than a distance between the first fin structure (F1) and the second fin structure (F2) (see Kim’193, Fig.6 as shown below and ¶ [0038]) .
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim, Sung, and Kim’193 to enable the combination of Kim’s and Sung’s fin structure to include a fourth fin structure adjacent to the third fin structure, wherein a distance between the third fin structure and the fourth fin structure to be greater than a distance between the first fin structure and the second fin structure as taught by Kim’193 in order to improve the electrical characteristic of the fin structure.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2017/0125597 A1, hereinafter refer to Kim) and Sung et al. (U.S. 2016/0071932 A1, hereinafter refer to Sung) as applied to claim 1 above, and further in view of Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung’613).
Regarding Claim 8: Kim discloses a fin field effect transistor (FinFET) device structure as applied to claim 1 above. Kim further teaches wherein a gate electrode layer (200) formed on the gate dielectric layer (130/140) (see Kim, Figs.6 and 8 as shown above).
Kim is silent upon explicitly disclosing wherein a portion of the gate electrode layer is lower than a top surface of the first liner layer.
For support see Sung’613, which teaches wherein a portion of the gate electrode layer (150) is lower than a top surface of the first liner layer (132) (see Sung’613, Fig.2 as shown below and ¶ [0004]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim, Sung, and Sung’613 to enable the Kim portion of the gate electrode layer to be lower than a top surface of the first liner layer as taught by Sung’613 in order to improve the performance of a highly integrated fin field effect transistor (FET).
Claim(s) 9-17 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. 2017/0125597 A1, hereinafter refer to Kim) in view of Kim et al. (U.S. 2016/0315193 A1, hereinafter refer to Kim’193).
Regarding Claim 9: Kim discloses a fin field effect transistor (FinFET) device structure (see Figs.6A-6B and 8-9 as shown above and ¶ [0007]), comprising:
a first fin structure (F2) extending above a substrate (100) (see Kim, Figs.6 and 8 as shown above);
a second fin structure (F1) adjacent to the first fin structure (F2), wherein the first fin structure (F2) comprises an inner sidewall surface close to the second fin structure (F1) and an outer sidewall surface away from the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above);
a third fin structure (F3) adjacent to the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above);
a first liner layer (L2) formed on the inner sidewall surface of the first fin structure (F2) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]);
a second liner layer (L2) formed on the outer sidewall surface of the first fin structure (F2) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]);
a first isolation structure (110) surrounded by the first liner layer (L2) (see Kim, Figs.6 and 8 as shown above); and
a second isolation structure (120) surrounded by the second liner layer (L2), wherein a width of the second isolation structure (120) is greater than a width of the first isolation structure (110) (see Kim, Figs.6 and 8 as shown above).
a first gate dielectric layer (130) formed on the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above); and
a second gate dielectric layer (130) formed on the third fin structure (F3) (see Kim, Figs.6 and 8 as shown above),
the first gate dielectric layer (130) is separated from the second gate dielectric layer (130) (see Kim, Figs.6 and 8 as shown above).
Kim is silent upon explicitly disclosing wherein the first gate dielectric layer and the second gate dielectric layer interfaces with the second isolation structure.
For support see Kim ‘193, which teaches wherein the first gate dielectric layer (310) and the second gate dielectric layer (310) interfaces with the second isolation structure (205) (see Kim’193, Figs.6 and 15 as shown below and ¶ [0038]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Kim’193 to enable the first gate dielectric layer and the second gate dielectric layer of Kim to be interfaces with the second isolation structure as taught by Kim’193 in order to improve the electrical characteristic of the fin structure.
Regarding Claim 10: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 9 as above. The combination of Kim and Kim’193 further teaches wherein a height of the second isolation structure (120) is smaller than a height of the first isolation structure (110) (see Kim, Fig.8 as shown above).
Regarding Claim 11: Kim as modified teaches a fin field effect transistor (FinFET) device structure as applied to claim 10 above. The combination of Kim and Kim’193 further teaches wherein the first fin structure (F1) has a bottom portion and a top portion, the bottom portion (102f) and the top portion (103f) of the first fin structure (F1) are made of different materials, and a first interface is between the top portion (103f) and the bottom portion (102f) (see Kim’193, Fig.6 as shown above and ¶ [0037]- ¶ [0038]).
Regarding Claim 12: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 11 as above. The combination of Kim and Kim’193 further teaches wherein the first interface is higher than a top surface of the second isolation structure (isolation region between F1 and F3) (see Kim’193, Fig.6 as shown above).
Regarding Claim 13: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 11 as above. The combination of Kim and Kim’193 further teaches wherein a top surface of the first isolation structure (isolation region between F1 and F2) is closer to the first interface than the second isolation structure (isolation region between F1 and F3) (see Kim’193, Fig.6 as shown above).
Regarding Claim 14: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 11 as above. The combination of Kim and Kim’193 further teaches wherein a gate dielectric layer (320) formed over the first fin structure, wherein a portion of the gate dielectric layer (320) is lower than the first interface (see Kim’193, Fig.6 as shown above and Fig.2C).
Regarding Claim 15: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 14 as above. The combination of Kim and Kim’193 further teaches wherein a sidewall surface of the gate dielectric layer (130/140) is aligned with a sidewall surface of the first liner layer (L2) (note: Kim is silent to demonstrate the arrangements of gate dielectric layer with relative to liner layer. Kim demonstrates the arrangements of gate dielectric layer with relative to field isolation film which teaches the sidewall surface of the gate dielectric layer (130/140) is aligned with a sidewall surface of the first filed isolation film (ST2/110). Since, the first liner layer (L2) formed on a first sidewall surface of the first fin structure and protruding above the top surface of filed isolation film 110 as demonstrated in Fig.6 as shown above, ordinary skill in the art recognize that the Kim sidewall surface of the gate dielectric layer necessarily aligned with a sidewall surface of the first liner layer as specified now in claim 1. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein a sidewall surface of the gate dielectric layer (124) is aligned with a sidewall surface of the first liner layer (132)) (see Kim, Figs.6 and 8 as shown above).
Regarding Claim 16: Kim discloses a fin field effect transistor (FinFET) device structure (see Figs.6A-6B and 8-9 as shown above and ¶ [0007]), comprising:
a first fin structure (F2) extending above a substrate (100), wherein the first fin structure (F2) has a bottom portion (F2L/F2U1) and a top portion (F2U2), and a first interface (S2) is between the top portion (F2U2) and the bottom portion (F2L/F2U1) (see Kim, Figs.6 and 8 as shown above);
a second fin structure (F1) adjacent to the first fin structure (F2), wherein the first fin structure (F2) comprises an inner sidewall surface close to the second fin structure (F1) and an outer sidewall surface away from the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above);
a first U-shaped liner layer (L2) formed on the inner sidewall surface of the first fin structure (F2) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (note: since, the STI structure has a U-shaped structure, the first liner layer L2 necessarily have a U-shaped structure. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein the first liner layer (132) has a U-shaped structure) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]); and
a second U-shaped liner layer (L2) formed on the outer sidewall surface of the first fin structure (F2), wherein a width of the second U-shaped liner layer (L2, at ST3 or ST1 region) is greater than a width of the first U-shaped liner layer (L2, at ST2 region) (note: “insulating liner L2 formed between the liner L1, and the first to the third fin-type patterns F1-F3”) (note: since, the STI structure has a U-shaped structure, the first liner layer L2 necessarily have a U-shaped structure. For support see Sung et al. (U.S. 2017/0062613 A1, hereinafter refer to Sung), Fig.2, which teaches wherein the first liner layer (132) has a U-shaped structure) (see Kim, Figs.6 and 8 as shown above and ¶ [0114]- ¶ [0115]); and
a first isolation structure (L1/120) surrounded by the first U-shaped liner layer (L2), wherein the first interface interfaces (S2) with first U-shaped liner layer (L2) (see Kim, Figs.6 and 8 as shown above).
Kim is silent upon explicitly disclosing wherein the bottom portion and the top portion of the first fin structure are made of different materials.
For support see Kim’193, which teaches wherein the bottom portion (102f) and the top portion (103f) of the first fin structure (F1) are made of different materials (see Kim’193, Fig.6 as shown above and ¶ [0037]- ¶ [0038]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Kim’193 to enable the Kim’s fin structure to include a bottom portion and a top portion, the bottom portion and the top portion of the first fin structure to be made of different materials as taught by Kim’193 in order to improve the electrical characteristic of the fin structure.
Regarding Claim 17: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 16 as above. The combination of Kim and Kim’193 further teaches wherein a second isolation structure (120) surrounded by the second U-shaped liner layer (L2) (see Kim, Figs.6 and 8 as shown above); and
a gate dielectric layer (130/140) formed on the first isolation structure (110) and the second isolation structure (120) (see Kim, Figs.6 and 8 as shown above).
First embodiment Fig.8 of Kim is silent upon explicitly disclosing wherein a portion of the second isolation structure is not covered by the gate dielectric layer.
Second embodiment of Kim teaches wherein a portion of the second isolation structure (120/150) is not covered by the gate dielectric layer (130/141/142) (see Kim, Figs.12-13).
Hence, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of first and second embodiment of Kim to enable portion of the second isolation structure is not covered by the gate dielectric layer in order to ensure spacing margin has to be ensured between the first gate electrode and the second gate electrode.
Regarding Claim 19: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 16 as above. The combination of Kim and Kim’193 is silent upon explicitly disclosing wherein the first liner layer is closer to the first interface than the second liner layer.
However, practicing the combination of Kim and Kim’193 to modify the Kim’s fin structure to include a bottom portion and a top portion, the bottom portion and the top portion of the first fin structure to be made of different materials, and a first interface between the top portion and the bottom portion and the first isolation structure to be closer to the first interface than the second isolation structure according to the teachings of Kim’s’193 necessarily results the claimed limitation of “the first liner layer is closer to the first interface than the second liner layer” as now specified in claim 19.
Regarding Claim 20: Kim discloses a fin field effect transistor (FinFET) device structure as applied to claim 16 above. Kim further teaches wherein a third fin structure (F3) adjacent to the second fin structure (F1) (see Kim, Figs.6 and 8 as shown above);
a third U-shaped liner layer (L2) formed between the fins structure (see Kim, Figs.6 and 8 as shown above).
Kim is silent upon explicitly disclosing wherein a fourth fin structure adjacent to the third fin structure.
For support see Kim’193, which teaches wherein a third fin structure (F3) adjacent to the second fin structure (F2) (see Kim’193, Fig.6 as shown above and ¶ [0038]);
a fourth fin structure (F4) adjacent to the third fin structure (F3) (see Kim’193, Fig.6 as shown above and ¶ [0038]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Kim and Kim’193 to enable the Kim fin structure to include a fourth fin structure adjacent to the third fin structure, wherein a distance between the third fin structure and the fourth fin structure to be greater than a distance between the first fin structure and the second fin structure as taught by Kim’193 in order to improve the electrical characteristic of the fin structure.
The combination of Kim and Kim’193 is silent upon explicitly disclosing wherein a third U-shaped liner layer formed between the third fin structure and the fourth fin structure, wherein a width of the third U-shaped liner layer is greater than the width of the first U-shaped liner layer and smaller than the width of the second U-shaped liner layer.
However, practicing the combination of Kim and Kim’193 to modify the Kim’s fin structure to include a fourth fin structure adjacent to the third fin structure, wherein a distance between the third fin structure and the fourth fin structure to be greater than a distance between the first fin structure and the second fin structure according to the teachings of Kim’s ‘193 necessarily results the claimed limitation of “a third U-shaped liner layer formed between the third fin structure and the fourth fin structure, wherein a width of the third U-shaped liner layer is greater than the width of the first U-shaped liner layer and smaller than the width of the second U-shaped liner layer” as now specified in claim 20.
Regarding Claim 21: Kim as modified teaches a fin field effect transistor (FinFET) device structure as set forth in claim 16 as above. The combination of Kim and Kim’193 further teachers wherein the first interface is far away from second U-shaped liner layer (note: the Kim’s isolation structure 200 is equivalent to the claimed limitation of separable “U-shaped liner” and “isolation structure” because mere duplication of insulating layers has no patentable significance unless a new and unexpected result is produced) (see Kim’193, Fig.6 as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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