Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I and species A (Figs. 1-5, 8-11, 13-15 and 21-25) in the reply filed on 08/04/2026 is acknowledged.
Claims 6, 7 and 12 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/04/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/27/2024 and 03/21/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-9, 11-15 and 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (US 2022/0115514).
As for claim 1, Jung et al. disclose in Figs. 1-23 and the related text a semiconductor device comprising:
a substrate 100;
a first channel region (left 124) and a second channel region (right 124) over the substrate (Fig. 1a-4);
a gate structure 320, wherein the gate structure is on one or more sidewalls of the first channel region and on one or more sidewalls of the second channel region (Fig. 2); and
a dielectric spacer 185/220/300 on a first side and a second side of the gate structure in a top- down view (Fig. 1), wherein the first side opposes the second side, and wherein a first portion of the dielectric spacer extends between the first channel region and the second channel region (Fig. 1-3).
As for claim 2, Jung et al. disclose the semiconductor device of claim 1, further comprising a first dielectric layer 290/300 on a first sidewall of the first channel region, wherein the first portion of the dielectric spacer is on the first dielectric layer (Fig. 1-2), wherein the gate structure 320 is on a second sidewall of the first channel region, and wherein the first sidewall opposes the second sidewall (Fig. 1-2).
As for claim 3, Jung et al. disclose the semiconductor device of claim 1, wherein the gate structure 300 wraps around the first portion of the dielectric spacer (Fig. 2).
As for claim 4, Jung et al. disclose the semiconductor device of claim 3, wherein the gate structure 300 wraps around the first channel region and the second channel region (Fig. 2).
As for claim 5, Jung et al. disclose the semiconductor device of claim 3, wherein the first channel region and the second channel region are top portions of fin structures protruding from the substrate (Fig. 3).
As for claim 8, Jung et al. disclose the semiconductor device of claim 1, further comprising a source/drain region 250 in contact with the first channel region, wherein a second portion of the dielectric spacer extends on a lower sidewall of the source/drain region (Fig. 3).
As for claim 9, Jung et al. disclose in Figs. 1-23 and the related text a semiconductor device comprising:
a substrate 100;
a first channel region 124 over the substrate;
a gate structure 300, wherein the gate structure is on a top surface and one or more sidewalls of the first channel region (Fig. 2-3); and
an insulating spacer 185/220/300, wherein a first portion (left 185) of the insulating spacer is on a first side of the gate structure and a second portion (upper portion of right 185) of the insulating spacer is on a second side of the gate structure in a top-down view (Fig. 1), wherein the first side opposes the second side (Fig. 1), wherein a third portion (lower portion of right 185) of the insulating spacer extends through the gate structure in the top-down view (fig. 1), and wherein the third portion of the insulating spacer is in (thermally) contact with the first portion and the second portion of the insulating spacer (Fig. 1-3).
As for claim 11, Jung et al. disclose the semiconductor device of claim 9, further comprising a fin structure 105 protruding from the substrate (Fig. 3), wherein the first channel region is over the fin structure, and wherein the gate structure extends between the fin structure and the first channel region (Fig. 3).
As for claim 13, Jung et al. disclose the semiconductor device of claim 9, further comprising a semiconductor dummy structure 105 underneath the third portion of the insulating spacer (Fig. 3), wherein the semiconductor dummy structure comprises amorphous silicon [0027].
As for claim 14, Jung et al. disclose the semiconductor device of claim 9, wherein the third portion 220/300 of the insulating spacer extends along a sidewall (lower side) of the first channel region, and wherein the third portion of the insulating spacer and the first channel region extend through a same opening in the gate structure (Fig. 3).
As for claim 15, Jung et al. disclose the semiconductor device of claim 14, further comprising a semiconductor dummy structure 105 underneath the third portion of the insulating spacer 220/300, wherein the semiconductor dummy structure comprises polycrystalline silicon [0027].
As for claim 21, Jung et al. disclose in Figs. 1-23 and the related text a semiconductor device comprising:
a first nanostructure 124;
a gate structure 300 around the first nanostructure (Fig. 2); and
a dielectric spacer 185/220/300, wherein a first portion (left 185) of the dielectric spacer is on a first side of the gate structure in a top-down view, wherein a second portion (upper portion of right 185) of the dielectric spacer is on a second side of the gate structure in the top-down view (Fig. 1), wherein a third portion 220/300 of the dielectric spacer is along a first sidewall (lower side) of the first nanostructure, and wherein the gate structure is around the third portion of the dielectric spacer (Fig. 2).
As for claim 22, Jung et al. disclose the semiconductor device of claim 21, wherein the third portion of the dielectric spacer has a convex sidewall in contact with the gate structure (Fig. 3)
As for claim 23, Jung et al. disclose the semiconductor device of claim 21, further comprising a second nanostructure (upper/lower) beside the first nanostructure, wherein the third portion of the dielectric spacer is between the first nanostructure and the second nanostructure (fig. 3).
As for claim 24, Jung et al. disclose the semiconductor device of claim 21, wherein the third portion 220/300 of the dielectric spacer extends through the gate structure in the top-down view (fig. 1), and wherein the third portion of the dielectric spacer is (thermally) connected to the first portion of the dielectric spacer and the second portion of the dielectric spacer (Fig. 1-3).
As for claim 25, Jung et al. disclose the semiconductor device of claim 21, further comprising a dielectric structure 290 between the first sidewall of the first nanostructure and the third portion of the dielectric spacer (Fig. 3), and wherein the gate structure is around the dielectric structure (Fig. 2).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al..
10. (Original) The semiconductor device of claim 9, wherein the first portion, the second portion, and the third portion of the insulating spacer form a shape of an "H" in the top-down view.
It would have been obvious to one of ordinary skill in the art at the time of the invention was made to provide the first portion, the second portion, and the third portion of the insulating spacer form a shape of an "H" in the top-down view in Jung et al., order to achieve the device properties.
Furthermore, the change in shape of the first portion, the second portion, and the third portion was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the first portion, the second portion, and the third portion was significant. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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