DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 2, 4 - 6, 11, 13, 17 - 19 are rejected under 35 U.S.C. 103 as being unpatentable over SHIBATA (20120268978) in view of KONNO et al. (20160035420).
With regard to claim 1, SHIBATA discloses a semiconductor structure (for example, see fig. 99), comprising:
a first memory array (a first memory array having memory cells “C1” as annotated in fig. 99 below) in a first cache (a group cache memory having transistors 210, 211, and data storage circuits SA thereon, functioning as a first cache; for example, see paragraph [0361]),
the first memory array including a plurality of first memory cells (C1) arranged in rows (referred to as “M1” by examiner’s annotation shown in fig. 99 below) and columns (referred to as “N1” by examiner’s annotation shown in fig. 99 below; and inherently having more columns forming in the memory cells C1 in order to store more bits in the cells), M1 and N1 each being an integer;
a first bit line (referred to as “BLE1” by examiner’s annotation shown in fig. 99 below; wherein the first bit line “BLE1” including a plurality of bit portions BLE) coupled to a number of first memory cells (C1) in one of the rows (M1), the first bit line (BLE1) having a first width (referred to as “W1” by examiner’s annotation shown in fig. 99 below) measured along a direction perpendicular to a lengthwise direction of the first bit line (BLE1);
a second memory array (a second memory array having memory cells “C2” as annotated in fig. 99 below) in a second cache (another group cache memory having transistors 210, 211 thereon with second memory cells C2 and data storage circuits SA thereon, functioning as a second cache; for example, see paragraph [0361]), the second memory array including a plurality of second memory cells (C2) arranged in rows (referred to as “M2” by examiner’s annotation shown in fig. 99 below) and columns (referred to as “N2” by examiner’s annotation shown in fig. 99 below), M2 and N2 each being an integer; and
a second bit line (referred to as “BLE2” by examiner’s annotation shown in fig. 99 below; wherein the second bit line “BLE2” including a plurality of bit portions BLE) coupled to a number of second memory cells (C2) in one of the rows (M2), the second bit line (BLE2) having a second width (referred to as “W2” by examiner’s annotation shown in fig. 99 below) measured along a direction perpendicular to a lengthwise direction of the second bit line (BLE2), wherein N1 is smaller than N2.
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SHIBATA do not clearly disclose the first width of the first bit line is smaller than the second width of the second bit line.
However, KONNO et al. disclose the first width (referred to as “X1” by examiner’s annotation shown in fig. 1 below) of the first bit line (the first bit line 20n wherein the first bit line 20n is formed in the bit line group G3) is smaller than the second width (referred to as “X2” by examiner’s annotation shown in fig. 1 below) of the second bit line (the second bit line 20w wherein the second bit line 20w is formed in the bit line group G4).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIBATA’s device to have the first width of the first bit line is smaller than the second width of the second bit line as taught by KONNO et al. in order to improve the information read speed and write speed by decreasing the parasitic capacitance formed between adjacent bit lines for enhancing a high storage capacity efficiency, as is known to one of ordinary skill in the art.
With regard to claim 2, SHIBATA discloses wherein M1 is smaller than M2 (as shown in fig. 99 above).
With regard to claim 4, SHIBATA discloses the first cache (the group cache memory having transistors 210, 211 thereon, functioning as the first cache; for example, see paragraph [0361]) is a level-1 cache (any level-1 cache functions as a level-1 cache), and the second cache (another group cache memory having transistors 210, 211 thereon with second memory cells C2, functioning as a second cache; for example, see paragraph [0361]) is a level-2 cache (any level-2 cache functions as a level-2 cache).
With regard to claim 5, SHIBATA discloses the first cache (the group cache memory having transistors 210, 211 thereon, functioning as the first cache; for example, see paragraph [0361]) and the second cache (another group cache memory having transistors 210, 211 thereon with second memory cells C2, functioning as a second cache; for example, see paragraph [0361]) are at a same cache level, and the first cache has a memory capacity smaller than the second cache (a number of the first cache memory cells C1 is smaller than a number of the second cache memory cells C2, so the first cache has a memory capacity smaller than the second cache).
With regard to claim 6, SHIBATA discloses N1 is less than 128 (column N1, as shown in fig. 99 above, is one or more is less than 128), and N2 is not less than 128 (column N2, as shown in fig. 99 above, is two or more is less than 128).
With regard to claim 11, SHIBATA discloses a semiconductor structure (for example, see fig. 99), comprising:
a first memory array (a first memory array having memory cells “C1” as annotated in fig. 99 below) disposed in a first region (a first region having memory cells “C1”) of the semiconductor structure,
the first memory array having a plurality of first memory cells (C1 as annotated in fig. 99 below), the first memory array including a first bit line (referred to as “BLE1” by examiner’s annotation shown in fig. 99 below; wherein the first bit line “BLE1” including a plurality of bit portions BLE) electrically coupled to a first number of the first memory cells (C1); and
a second memory array (a second memory array having memory cells “C2” as annotated in fig. 99 below) disposed in a second region (a second region having memory cells “C2”) of the semiconductor structure, the second memory array having a plurality of second memory cells (C2 as annotated in fig. 99 below),
the second memory array including a second bit line (referred to as “BLE2” by examiner’s annotation shown in fig. 99 below; wherein the second bit line “BLE2” including a plurality of bit portions BLE) electrically coupled to a second number of the second memory cells (C2), wherein the first number (the first number of the first memory cells C1) is smaller than the second number (the second number of the second memory cells C2), and a width (referred to as “W1” by examiner’s annotation shown in fig. 99 below) of the first bit line (BLE1) measured along a direction perpendicular to a lengthwise direction of the first bit line (BLE1) and a width (referred to as “W2” by examiner’s annotation shown in fig. 99 below) of the second bit line (BLE2) measured along a direction perpendicular to a lengthwise direction of the second bit line (BLE2).
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SHIBATA do not clearly disclose the first width of the first bit line is smaller than the second width of the second bit line.
However, KONNO et al. disclose the first width (referred to as “X1” by examiner’s annotation shown in fig. 1 below) of the first bit line (the first bit line 20n wherein the first bit line 20n is formed in the bit line group G3) is smaller than the second width (referred to as “X2” by examiner’s annotation shown in fig. 1 below) of the second bit line (the second bit line 20w wherein the second bit line 20w is formed in the bit line group G4).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIBATA’s device to have the first width of the first bit line is smaller than the second width of the second bit line as taught by KONNO et al. in order to improve the information read speed and write speed by decreasing the parasitic capacitance formed between adjacent bit lines for enhancing a high storage capacity efficiency, as is known to one of ordinary skill in the art.
With regard to claim 13, SHIBATA discloses the first region (the first region having first memory cells C1) is a level-1 cache (any level-1 cache functions as a level-1 cache), and the second region (the second region having second memory cells C2) is a level-2 cache (any level-2 cache functions as a level-2 cache).
With regard to claim 17, SHIBATA discloses a first input/output region (a region, having data storage circuits SA, fig. 99 or 10, fig. 64 acts as first input/out region by maintaining a state that can be written to input and read output) coupled to the first memory array (the array having first cells C1), wherein the first bit line extends continuously into the first I/O region; and a second I/O region (another region, having data storage circuits SA, fig. 99 or 10, fig. 64 acts as second input/out region by maintaining a state that can be written to input and read output) coupled to the second memory array (the array having first cells C2), wherein the second bit line extends continuously into the second I/O region.
With regard to claim 18, SHIBATA discloses a method of forming a memory circuit (for example, see fig. 99), comprising:
forming a first memory array (a first memory array having memory cells “C1” as annotated in fig. 99 below) in a first cache located (a group cache memory having transistors 210, 211 thereon, functioning as a first cache; for example, see paragraph [0361]) in the memory circuit, the first memory array including a plurality of first memory cells (C1);
forming a second memory array (a second memory array having memory cells “C2” as annotated in fig. 99 below) in a second cache (another group cache memory having transistors 210, 211 thereon with second memory cells C2, functioning as a second cache; for example, see paragraph [0361]) located in the memory circuit, the second memory array including a plurality of second memory cells (C2);
forming a first bit line (referred to as “BLE1” by examiner’s annotation shown in fig. 99 below; wherein the first bit line “BLE1” including a plurality of bit portions BLE) suspended over (for example, see fig. 97, 99) the first memory array (the first memory array having memory cells “C1” as annotated in fig. 99 below), the first bit line (BLE1) being coupled to at least a portion of the first memory cells (C1); and forming a second bit line (referred to as “BLE2” by examiner’s annotation shown in fig. 99 below; wherein the second bit line “BLE2” including a plurality of bit portions BLE) suspended over (for example, see fig. 97, 99) the second memory array (a second memory array having memory cells “C2” as annotated in fig. 99 below), the second bit line (BLE2) being coupled to at least a portion of the second memory cells (C2), wherein a width (referred to as “W1” by examiner’s annotation shown in fig. 99 below) of the first bit line (BLE1) measured along a direction perpendicular to a lengthwise direction of the first bit line (BLE1) and a width (referred to as “W2” by examiner’s annotation shown in fig. 99 below) of the second bit line (BLE2) measured along a direction perpendicular to a lengthwise direction of the second bit line (BLE2).
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SHIBATA do not clearly disclose the first width of the first bit line is different from the second width of the second bit line.
However, KONNO et al. disclose the first width (referred to as “X1” by examiner’s annotation shown in fig. 1 below) of the first bit line (the first bit line 20n wherein the first bit line 20n is formed in the bit line group G3) is different from the second width (referred to as “X2” by examiner’s annotation shown in fig. 1 below) of the second bit line (the second bit line 20w wherein the second bit line 20w is formed in the bit line group G4).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIBATA’s device to have the first width of the first bit line is different from the second width of the second bit line as taught by KONNO et al. in order to improve the information read speed and write speed by decreasing the parasitic capacitance formed between adjacent bit lines for enhancing a high storage capacity efficiency, as is known to one of ordinary skill in the art.
With regard to claim 19, SHIBATA discloses the first memory array (C1) is smaller than the second memory array (C2), and the width (W1) of the first bit line (BLE1) is smaller than the width (W2) of the second bit line (BLE2).
Claims 3, 20 are rejected under 35 U.S.C. 103 as being unpatentable over SHIBATA (20120268978) in view of KONNO et al. (20160035420) and further in view of Lee (11768625).
With regard to claims 3, 20, SHIBATA discloses the first cache has a memory capacity smaller than the second cache (the first memory array C1 is smaller than the second memory array C2, so the first cache of the first memory array C1 has a memory capacity smaller than the second cache of the second memory array C2), but SHIBATA does not clearly disclose the first cache has a speed faster than the second cache.
However, Lee discloses the first cache has a speed faster than the second cache. (the first cache memory 310 may be a memory operating at a speed higher than that of the second cache memory 320). (for example, see column 5, lines 17 – 21, and column 8, lines 26 – 27, fig. 5).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIBATA and KONNO et al.’s device to have the first cache has a speed faster than the second cache as taught by Lee in order to enhance a high-speed efficiency of the semiconductor memory device, as is known to one of ordinary skill in the art.
Claims 7, 8 are rejected under 35 U.S.C. 103 as being unpatentable over SHIBATA (20120268978) in view of KONNO et al. (20160035420) and further in view of CHUANG et al. (20220029093).
With regard to claim 7, SHIBATA disclose the first memory cells (C1) each inherently have a first cell width and a first cell height, the second memory cells (C2) each inherently have a second cell width and a second cell height, but SHIBATA does not clearly disclose the first cell height is larger than the second cell height.
However, CHUANG et al. disclose the first cell height (a height of the first cell MC1) is larger than the second cell height (a height of the second cell MC2). (for example, see paragraph [0070], fig. 19 discloses the memory cells MC1 and MC2 may have different heights, so it is inherently a height of the first cell MC1 is larger than a height of the second cell MC2).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIBATA and KONNO et al.’s device to have the first cell height is larger than the second cell height as taught by CHUANG et al. in order to enhance a high-storage capacity efficiency of the semiconductor memory device, as is known to one of ordinary skill in the art.
With regard to claim 8, CHUANG et al. disclose the first cell width equals the second cell width (the memory cells MC1 and MC2 may have different widths. Therefore, it is inherently ones of the memory cells MC1 and MC2 can have same widths). (for example, see paragraph [0070]).
Claims 9, 10, 15 are rejected under 35 U.S.C. 103 as being unpatentable over SHIBATA (20120268978) in view of KONNO et al. (20160035420) and further in view of Ichige et al. (7649777).
With regard to claims 9, 10, 15, SHIBATA does not clearly disclose the first or second memory array includes a first active region for n-type transistors in the first memory cells, and a ratio of the first or second width of the bit-line and a width of the first or second active region is about 1.5.
However, Ichige et al. disclose the first or second memory array includes a first active region (channel region 12) for n-type transistors in the first memory cells, and a ratio of the first or second width (referred to as “W1” by examiner’s annotation shown in fig. 7 below) of the bit-line (BL) and a width (referred to as “W2” by examiner’s annotation shown in fig. 7 below) of the first or second active region (12) is about 1.5.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIBATA and KONNO et al.’s device to have the first or second memory array includes a first active region for n-type transistors in the first memory cells, and a ratio of the first or second width of the bit-line and a width of the first or second active region is about 1.5 as taught by Ichige et al. in order to enhance electrical contact between the bit line and source/drain region of the semiconductor memory device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over SHIBATA (20120268978) in view of KONNO et al. (20160035420) and further in view of Huang et al. (20240404587).
With regard to claim 12, SHIBATA does not clearly disclose the first and second memory cells are static random-access memory cells.
However, Huang et al. disclose the first and second memory cells (each of SRAM cell regions R1, R2, R3, R4 arranged in an array to form the layout pattern of SRAM) are static random-access memory cells. (for example, see paragraph [0051], fig. 5).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIBATA and KONNO et al.’s device to have the first and second memory cells are static random-access memory cells as taught by Huang et al. in order to enhance a high storage capacity efficiency of the semiconductor memory device, as is known to one of ordinary skill in the art.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over SHIBATA (20120268978) in view of KONNO et al. (20160035420) and further in view of Arunkumar et al. (12182028).
With regard to claim 14, SHIBATA does not clearly disclose the first number is 64, and the second number is 128.
However, Huang et al. disclose the first number is 64, and the second number is 128. (for example, see column 18, lines 27 – 40 disclose each of the first cache device and the second cache device are configured for a block-by-block storage process according to a predetermined block size 16, 64, 128, so the first cache device functions as the first memory device having a number 64 and the second cache device functions as the second memory device having a number 128).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIBATA and KONNO et al.’s device to have the first number is 64, and the second number is 128 as taught by Arunkumar et al. in order to improve the stability and performance of the memory cells for enhancing a high storage capacity efficiency, as is known to one of ordinary skill in the art.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over SHIBATA (20120268978) in view of KONNO et al. (20160035420) and further in view of Liaw (9218872).
With regard to claim 16, SHIBATA does not clearly disclose the first memory cells each have a first active region for n-type transistors, the second memory cells each have a second active region for n-type transistors, and a width of the first active region is larger than a width of the second active region.
However, Liaw discloses the first memory cells (first SRAM cells of Liaw functions as the first memory cells) each have a first active region for n-type transistors (PD transistors), the second memory cells (second SRAM cells of Liaw functions as the second memory cells) each have a second active region for n-type transistors (PD transistors), and a width of the first active region is larger than a width of the second active region. (claim 9 discloses the PD transistor of each cell of the plurality of first SRAM cells comprises a first channel width, and the PD transistor of each cell of the plurality of second SRAM cells comprises a second channel width; wherein the first channel width is wider than the second channel width by at least 10%).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SHIBATA and KONNO et al.’s device to have the first memory cells each have a first active region for n-type transistors, the second memory cells each have a second active region for n-type transistors, and a width of the first active region is larger than a width of the second active region as taught by Liaw in order to enhance a high electron mobility efficiency of the channel region, as is known to one of ordinary skill in the art.
Response to Amendment
9. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
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