DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on May 26, 2026.
Claims 1-17 and 21-23 are pending. Claim 18-20 are canceled. Claims 1, 2-6, 10-13, 15-17, 21 and 23 are amended. Claims 1, 11 and 21 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on May 26, 2026. These drawings are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8-9 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210305262) in view of Hsu et al. (US 20210375883).
Regarding independent claim 1, Wang et al. disclose a method, comprising:
forming a static random access memory (SRAM) array in a device layer, wherein the SRAM array comprises a first SRAM cell and a second SRAM cell adjacent to the first SRAM cell, and from a top view, the first and second SRAM cells are arranged in a first direction [see Fig. 2 as well as Fig. 4A, FIG. 2 illustrates memory cells laid out in a set of columns 202a, 202b, 202c, 202d, and rows 204a, 204b, 204c, 204d, para. 26. Fig. 4A illustrates layout of memory cells 401, 403 for an SRAM memory cell layout. It is noted that cell 403 is symmetric (reflected across y-axis) to cell 401, para. 37];
forming a first word line over a front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37] and extending across the first and second SRAM cells in the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26], wherein the first word line is electrically coupled to the first SRAM cell [see Fig. 2, memory cell 210 is positioned within column 202b and row 204a, para. 27. The memory cell 210 connects only to one of the two word lines 208a, 208b. Specifically, memory cell 210 connects to word line 208a, para. 28]; and
forming a bit line and a bit line bar over a back-side of the device layer, wherein the first and second SRAM cells share the bit line and the bit line bar [FIG. 4B illustrates the layout of the memory cells 401, 403 with respect to the backside of the substrate. Both of the BL and BLB lines on both sides of the memory cells 401, 403 are shared with adjacent memory cells in adjacent columns, para. 38].
However, Wang et al. are silent with respect to wherein the first SRAM cell comprises four gate structures, each of the four gate structures having a longitudinal dimension extending along the first direction, the four gate structures being arranged along a second direction transverse to the first direction, and wherein each of the four gate structures is spaced apart from an adjacent one of the four gate structures along the second direction.
Hsu et al. teach the first SRAM cell [Fig. 4A: 120] comprises four gate structures [Fig. 4A: 218-1, 218-2, 218-3, and 218-4], each of the four gate structures having a longitudinal dimension extending along the first direction [the SRAM cell 120 includes four gates 218-1, 218-2, 218-3, and 218-4 oriented lengthwise along the “x” direction in FIG. 4A, para. 23], the four gate structures being arranged along a second direction transverse to the first direction, and wherein each of the four gate structures is spaced apart from an adjacent one of the four gate structures along the second direction [see Fig. 6, the gates 218 are arranged as rectangular pieces and spaced from each other with the same spacing among them along the “y” direction, para. 30].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Hsu et al. to the teaching of Wang et al. such that implementing shared bit line SRAM architecture of Wang et al. using four-poly-pitch SRAM cell layout of Hsu et al. to obtain a compact SRAM structure with predictable metal conductor's resistance-capacitance and routing benefits.
Regarding claim 2, Wang et al. in combination with Hsu et al. teach the limitations with respect to claim 1.
Furthermore, Wang et al. disclose further comprising:
forming a second word line over the front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37] and extending across the first and second SRAM cells in the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26], wherein the second word line is electrically coupled to the second SRAM cell [see Fig. 2, the adjacent memory cells within row 202a connect to word line 208b and do not connect with word line 208a, para. 28].
Regarding claim 3, Wang et al. in combination with Hsu et al. teach the limitations with respect to claim 1.
Furthermore, Wang et al. disclose wherein the bit line and the bit line bar extend along the second direction [see Fig. 2, bit lines (including bit lines 206a, 206b) are shown in dotted boxes extending parallel to the columns 202a, 202b, 202c, 202d while word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d, para. 26].
Regarding claim 4, Wang et al. in combination with Hsu et al. teach the limitations with respect to claim 1.
Furthermore, Wang et al. disclose wherein from the top view, a first dimension of the first SRAM cell measured in the first direction is less than a second dimension of the first SRAM cell measured in the second direction [Wang et al. disclose the bit lines are at least approximately 50% wider than the word lines. The width may be measured in the top view, para. 26. Moreover, Wang et al. also disclose word lines extend along a first direction while the bit line and the bit line bar extend along a second direction, thus a person of ordinary skill in the art would have found it obvious that a first dimension of the first SRAM cell measured in the first direction is less than a second dimension of the first SRAM cell measured in a second direction perpendicular to the first direction].
Regarding claim 8, Wang et al. in combination with Hsu et al. teach the limitations with respect to claim 1.
Furthermore, Wang et al. disclose further comprising:
forming a power rail over the back-side of the device layer, wherein the first and second SRAM cells share the power rail [see Fig. 4B, the power line Vdd is formed on the backside of the substrate and shared between adjacent cells 401 and 403, para. 37-38].
Regarding claim 9, Wang et al. in combination with Hsu et al. teach the limitations with respect to claim 8.
Furthermore, Wang et al. disclose wherein from the top view, the power rail extends in parallel with the bit line and the bit line bar [see Fig. 4B, the power line Vdd is parallel with the bit lines BL and BLB, para. 37-38].
Regarding independent claim 21, Wang et al. disclose a method, comprising:
forming a first word line over a front-side of a device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37], wherein the device layer comprises a first static random access memory (SRAM) cell and a second SRAM cell arranged along a first direction from a top view [see Fig. 2 as well as Fig. 4A, FIG. 2 illustrates memory cells laid out in a set of columns 202a, 202b, 202c, 202d, and rows 204a, 204b, 204c, 204d, para. 26. Fig. 4A illustrates layout of memory cells 401, 403 for an SRAM memory cell layout. It is noted that cell 403 is symmetric (reflected across y-axis) to cell 401, para. 37], and wherein the first word line extends along the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26] and electrically coupled to the first SRAM cell [see Fig. 2, memory cell 210 is positioned within column 202b and row 204a, para. 27. The memory cell 210 connects only to one of the two word lines 208a, 208b. Specifically, memory cell 210 connects to word line 208a, para. 28];
forming a second word line over the front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37], wherein the second word line extends along the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26] and electrically coupled to the second SRAM cell [see Fig. 2, the adjacent memory cells within row 202a connect to word line 208b and do not connect with word line 208a, para. 28];
forming a bit line over a back-side of the device layer [FIG. 4B illustrates the layout of the memory cells 401, 403 with respect to the backside of the substrate. Both of the BL and BLB lines on both sides of the memory cells 401, 403 are shared with adjacent memory cells in adjacent columns, para. 38], wherein the bit line extends along a second direction and is electrically coupled to the first and second SRAM cells [see Fig. 2, bit lines 206a is shown in dotted boxes extending parallel to the columns 202a, 202b, 202c, 202d. Connections from bit line 206a to a particular memory cell columns 202a, 202b are shown with filled in dots, para. 26]; and
forming a bit line bar over the back-side of the device layer and at a same level height as the bit line, wherein the bit line bar is electrically coupled to the first and second SRAM cells [FIG. 4B illustrates the layout of the memory cells 401, 403 with respect to the backside of the substrate. Both of the BL and BLB lines on both sides of the memory cells 401, 403 are shared with adjacent memory cells in adjacent columns, para. 38].
However, Wang et al. are silent with respect to wherein, from the top view, the first SRAM cell comprises four gate structures, each of the four gate structures having a longitudinal dimension extending along the first direction, the four gate structures being arranged along a second direction transverse to the first direction, and wherein each of the four gate structures is spaced apart from an adjacent one of the four gate structures along the second direction.
Hsu et al. teach the first SRAM cell [Fig. 4A: 120] comprises four gate structures [Fig. 4A: 218-1, 218-2, 218-3, and 218-4], each of the four gate structures having a longitudinal dimension extending along the first direction [the SRAM cell 120 includes four gates 218-1, 218-2, 218-3, and 218-4 oriented lengthwise along the “x” direction in FIG. 4A, para. 23], the four gate structures being arranged along a second direction transverse to the first direction, and wherein each of the four gate structures is spaced apart from an adjacent one of the four gate structures along the second direction [see Fig. 6, the gates 218 are arranged as rectangular pieces and spaced from each other with the same spacing among them along the “y” direction, para. 30].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Hsu et al. to the teaching of Wang et al. such that implementing shared bit line SRAM architecture of Wang et al. using four-poly-pitch SRAM cell layout of Hsu et al. to obtain a compact SRAM structure with predictable metal conductor's resistance-capacitance and routing benefits.
Regarding claim 22, Wang et al. in combination with Hsu et al. teach the limitations with respect to claim 21.
Furthermore, Wang et al. disclose further comprising:
forming a power rail over the back-side of the device layer and at the same level height as the bit line and the bit line bar, wherein the power rail is electrically coupled to the first and second SRAM cells, and from the top view, the power rail is between the bit line and the bit line bar [see Fig. 4B, the power line Vdd is formed on the backside of the substrate and shared between adjacent cells 401 and 403. The power line Vdd is between the bit line BL and the bit line bar BLB, para. 37-38].
Regarding claim 23, Wang et al. in combination with Hsu et al. teach the limitations with respect to claim 21.
Furthermore, Wang et al. disclose further comprising:
forming a first power rail over the front-side of the device layer and electrically couple to the first SRAM cell [Fig. 4A illustrates the via connections 402 from the active regions to the Vss power lines formed on the frontside of the substrate. The Vss lines may be shared with adjacent memory cells, para. 37]; and
forming a second power rail over the front-side of the device layer and electrically coupled to the second SRAM cell, wherein the first and second power rails extend along the second direction [Fig. 4A illustrates the via connections 402 from the active regions to the Vss power lines formed on the frontside of the substrate. The Vss lines may be shared with adjacent memory cells, para. 37], and from the top view, the bit line and the bit line bar are between the first and second power rails [see Fig. 5B, para. 43].
Claims 5-7, 10-12, 14-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210305262) in view of Hsu et al. (US 20210375883) and further in view of Fujiwara et al. (US 20210098467).
Regarding claims 5, Wang et al. in combination with Hsu et al. teach the limitations with respect to claim 1.
Furthermore, Wang et al. disclose the first and second SRAM cells each comprise first and second pass-gate transistors [see Fig. 1: PG1, PG2, para. 22 and 24] and method further comprises:
forming a first contact over the back-side of the device layer prior to the step of forming the bit line and the bit line bar [Fig. 4B: contacts 404, para. 38].
However, Wang et al. in combination with Hsu et al. are silent with respect to wherein the first contact extends from a first source/drain region of the first pass-gate transistor of the first SRAM cell to a second source/drain region of the first pass-gate transistor of the second SRAM cell, and the bit line is electrically coupled to the first and second SRAM cells through the first contact.
Fujiwara et al. teach a first contact extends from a first source/drain region of the first pass-gate transistor of the first SRAM cell to a second source/drain region of the first pass-gate transistor of the second SRAM cell, and the bit line is electrically coupled to the first and second SRAM cells through the first contact [see Fig. 7, the connection of the bit cells 410 and 450 to the bit line BL are made by the via 492, which is connected to the shared S/D contact 402, which is a shared S/D contact of both the pass gate PG0 transistors of both the bit cells 410 and 450, para. 50].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Fujiwara et al. to the teaching of Wang et al. in combination with Hsu et al. such that incorporating shared source/drain contact and via connection scheme as taught by Fujiwara et al. into the shared bit line SRAM architecture as taught by Wang et al. in combination with Hsu et al. to achieve predictable benefits – fewer contacts/vias per bit cell, reducing routing congestion and improving parasitic performance.
Regarding claims 6, Wang et al. in combination with Hsu et al. and Fujiwara et al. teach the limitations with respect to claim 5.
Furthermore, Hsu et al. disclose wherein, from the top view, the first contact has a first dimension extending in the first direction, and a second dimension extending in the second direction, and the first dimension is greater than the second dimension [see Fig. 4A, the SRAM cell 120 has a length of X/2 along the “x” direction and a width of 2Y along the “y” direction. The X and Y refer to the dimension of a 6-T transistor layout with two-poly pitch, which has a length of X along the “x” direction and a width Y along the “y” direction. In some embodiments, the ratio of X to Y is 2.5 to 1, para. 23].
Regarding claims 7, Wang et al. in combination with Hsu et al. and Fujiwara et al. teach the limitations with respect to claim 5.
Furthermore, Fujiwara et al. disclose further comprising:
forming a second contact over the back-side of the device layer prior to the step of forming the bit line and the bit line bar, wherein the second contact extends from a third source/drain region of the second pass-gate transistor of the first SRAM cell to a fourth source/drain region of the second pass-gate transistor of the second SRAM cell, and the bit line bar is electrically coupled to the first and second SRAM cells through the second contact [see Fig. 7, the connection of the bit cells 410 and 450 to the complementary bit line BLB are made by the via 496, which is connected to the shared S/D contact 406, which is a shared S/D contact of both the pass gate PG1 transistors of both the bit cells 410 and 45, para. 50].
Regarding claims 10, Wang et al. in combination with Hsu et al. teach the limitations with respect to claim 8.
Furthermore, Wang et al. disclose wherein the first and second SRAM cells each comprise first and second pull-down transistors [see Fig. 1: PD1, PD2, para. 22-24], and the method further comprises:
forming a contact over the back-side of the device layer prior to the step of forming the power rail [Fig. 4B: contacts 404, para. 38].
However, Wang et al. in combination with Hsu et al. are silent with respect to wherein the contact extends from a first source/drain region between the first and second pull-down transistors of the first SRAM cell to a second source/drain region between the first and second pull-down transistors of the second SRAM cell, and the power rail is electrically coupled to the first and second SRAM cells through the contact.
Fujiwara et al. teach the contact extends from a first source/drain region between the first and second pull-down transistors of the first SRAM cell to a second source/drain region between the first and second pull-down transistors of the second SRAM cell, and the power rail is electrically coupled to the first and second SRAM cells through the contact [see Fig. 7, the S/D contact 404 extends from the fin 414 in the negative Y-axis direction and is connected to the fin 454 between the poly 464 and the poly 466, and is connected to VSS in the M1 metal layer by the via 494. The first bit cell 410 and the second bit cell “share” the S/D contact 404. The PD0 and PD1 transistors share the S/D contact 404 and are thereby connected to the reference voltage VSS in the M1 layer, e.g. ground, para. 42].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Fujiwara et al. to the teaching of Wang et al. in combination with Hsu et al. such that incorporating shared source/drain contact and via connection scheme as taught by Fujiwara et al. into the shared bit line SRAM architecture as taught by Wang et al. in combination with Hsu et al. to achieve predictable benefits – fewer contacts/vias per bit cell, reducing routing congestion and improving parasitic performance.
Regarding independent claim 11, Wang et al. disclose a method, comprising:
forming a first static random access memory (SRAM) cell and a second SRAM cell in a device layer [see Fig. 2 as well as Fig. 4A, FIG. 2 illustrates memory cells laid out in a set of columns 202a, 202b, 202c, 202d, and rows 204a, 204b, 204c, 204d, para. 26. Fig. 4A illustrates layout of memory cells 401, 403 for an SRAM memory cell layout. It is noted that cell 403 is symmetric (reflected across y-axis) to cell 401, para. 37], wherein the first and second SRAM cell each comprises a first pass-gate transistor and a second pass-gate transistor [see Fig. 1: PG1, PG2, para. 22 and 24];
forming a first back-side contact [Fig. 4B: contacts 404, para. 38];
forming a second back-side contact [Fig. 4B: contacts 404, para. 38];
forming a first back-side via over the first back-side contact [see Fig. 5B, the semiconductor material of the active regions 504a, 504b, 504c at this cross-section have been replaced with conductive materials to allow contact to the associated transistor terminal, para. 43];
forming a second back-side via over the second back-side contact [see Fig. 5B, the semiconductor material of the active regions 504a, 504b, 504c at this cross-section have been replaced with conductive materials to allow contact to the associated transistor terminal, para. 43];
forming a bit line over the first back-side via [see Fig. 5B, there is a via 504b connecting the source/drain feature (of active region 502b) to the bit line BL, para. 43].
However, Wang et al. are silent with respect to wherein, from the top view, the first SRAM cell comprises four gate structures, each of the four gate structures having a longitudinal dimension extending along the first direction, the four gate structures being arranged along a second direction transverse to the first direction, and wherein each of the four gate structures is spaced apart from an adjacent one of the four gate structures along the second direction;
forming a first back-side contact extending from a first source/drain region of the first pass-gate transistor of the first SRAM cell to a second source/drain region of the first pass-gate transistor of the second SRAM cell;
forming a second back-side contact extending from a third source/drain region of the second pass-gate transistor of the first SRAM cell to a fourth source/drain region of the second pass-gate transistor of the second SRAM cell; and
forming a bit line bar over the second back-side via.
Hsu et al. teach the first SRAM cell [Fig. 4A: 120] comprises four gate structures [Fig. 4A: 218-1, 218-2, 218-3, and 218-4], each of the four gate structures having a longitudinal dimension extending along the first direction [the SRAM cell 120 includes four gates 218-1, 218-2, 218-3, and 218-4 oriented lengthwise along the “x” direction in FIG. 4A, para. 23], the four gate structures being arranged along a second direction transverse to the first direction, and wherein each of the four gate structures is spaced apart from an adjacent one of the four gate structures along the second direction [see Fig. 6, the gates 218 are arranged as rectangular pieces and spaced from each other with the same spacing among them along the “y” direction, para. 30].
Furthermore, Fujiwara et al. teach forming a first back-side contact extending from a first source/drain region of the first pass-gate transistor of the first SRAM cell to a second source/drain region of the first pass-gate transistor of the second SRAM cell [see Fig. 7, the connection of the bit cells 410 and 450 to the bit line BL are made by the via 492, which is connected to the shared S/D contact 402, which is a shared S/D contact of both the pass gate PG0 transistors of both the bit cells 410 and 450, para. 50];
forming a second back-side contact extending from a third source/drain region of the second pass-gate transistor of the first SRAM cell to a fourth source/drain region of the second pass-gate transistor of the second SRAM cell [see Fig. 7, the connection of the bit cells 410 and 450 to the complementary bit line BLB are made by the via 496, which is connected to the shared S/D contact 406, which is a shared S/D contact of both the pass gate PG1 transistors of both the bit cells 410 and 45, para. 50];
forming a first back-side via over the first back-side contact [see Fig. 7, the S/D contact 402 is connected to the bit line BL in the M1 metal layer by the via 492, para. 37];
forming a second back-side via over the second back-side contact [see Fig. 7, the S/D contact 406 is connected to the complementary bit line BLB in the M1 metal layer by the via 496, para. 37];
forming a bit line over the first back-side via [see Fig. 7, the connection of the bit cells 410 and 450 to the bit line BL are made by the via 492, para. 50]; and
forming a bit line bar over the second back-side via [see Fig. 7, the connection of the bit cells 410 and 450 to the complementary bit line BLB are made by the via 496, para. 50].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Hsu et al. and Fujiwara et al. to the teaching of Wang et al. such that incorporating four-poly-pitch SRAM cell layout of Hsu et al. and shared source/drain contacts and vias connection scheme as taught by Fujiwara et al. into Wang et al.’s shared bit line SRAM architecture to achieve predictable benefits – reducing metal conductor's resistance-capacitance, fewer contacts/vias per bit cell, reducing routing congestion and improving parasitic performance.
Regarding claims 12, Wang et al. in combination with Hsu et al. and Fujiwara et al. teach the limitations with respect to claim 11.
Furthermore, Wang et al. disclose further comprising:
forming a first word line over a front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37] and extending across the first and second SRAM cells along the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26]; and
forming a second word line over the front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37] and extending across the first and second SRAM cells along the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26], wherein the first word line is electrically coupled to the first SRAM cell [see Fig. 2, memory cell 210 is positioned within column 202b and row 204a, para. 27. The memory cell 210 connects only to one of the two word lines 208a, 208b. Specifically, memory cell 210 connects to word line 208a, para. 28], and the second word line is electrically coupled to the second SRAM cell [see Fig. 2, the adjacent memory cells within row 202a connect to word line 208b and do not connect with word line 208a, para. 28].
Regarding claims 14, Wang et al. in combination with Hsu et al. and Fujiwara et al. teach the limitations with respect to claim 11.
Furthermore, Wang et al. disclose further comprising:
forming a first power rail over a front-side of the device layer and extending along a cell boundary of the first SRAM cell [see Fig. 4A, the Vss lines are formed on the frontside of the substrate and shared with adjacent memory cells, para. 37].
Regarding claims 15, Wang et al. in combination with Hsu et al. and Fujiwara et al. teach the limitations with respect to claim 14.
Furthermore, Fujiwara et al. disclose wherein the first SRAM cell comprises a first pull-up transistor and a second pull-up transistor, and the first power rail is electrically coupled to a shared source/drain region between a first one of the four gate structures that serves as a gate structure of the first pull-up transistor and a second one of the four gate structures that serves as a gate structure of the second pull-up transistor [see Fig. 7, power is supplied on the VDD lines in the first metal layer M1, and is connected to the S/D contact 434 of both PU0 and PU1 of the first bit cell 410 by the via 441, para. 35].
Regarding claims 17, Wang et al. in combination with Hsu et al. and Fujiwara et al. teach the limitations with respect to claim 14.
Furthermore, Fujiwara et al. disclose further comprising:
forming a second power rail over a back-side of the device layer, wherein the second power rail is electrically couple to the first power rail and overlaps with the first power rail from the top view [see Fig. 7, the S/D contacts 434 and 474 are connected to a VDD line in the M1 layer by the vias 441 and 481, and the S/D contact 404 is connected to a VSS line in the M1 layer by the via 494, para. 60].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210305262) in view of Hsu et al. (US 20210375883) and Fujiwara et al. (US 20210098467) as applied to claim 11 above and further in view of Yang et al. (US 20220319583).
Regarding claim 13, Wang et al. in combination with Hsu et al. and Fujiwara et al. teach the limitations with respect to claim 11.
However, Wang et al. in combination with Hsu et al. and Fujiwara et al. are silent with respect to further comprising:
forming a dielectric gate in the device layer, wherein the dielectric gate is in contact with and aligned with one of the four gate structures that serves as a gate structure of the first pass-gate transistor of the first SRAM cell from the top view.
Yang et al. teach forming a dielectric gate in the device layer, wherein the dielectric gate is in contact with and aligned with one of the four gate structures that serves as a gate structure of the first pass-gate transistor of the first SRAM cell from the top view [see Fig. 4, the first metal gate cut feature 420A and the second metal gate cut feature 420B includes one or more dielectric material filled into a metal gate cut trench that completely severs the respective metal gate stack (406-1 or 406-2) that formed over the fin/fins active regions used for SRAM transistors, para. 30].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yang et al. to the teaching of Wang et al. in combination with Hsu et al. and Fujiwara et al. such that incorporating Yang et al.’s dielectric gate feature into SRAM layout of Wang et al. in combination with Hsu et al. and Fujiwara et al. to enhance isolation and process robustness without changing the fundamental SRAM electrical operation.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210305262) in view of Hsu et al. (US 20210375883) and Fujiwara et al. (US 20210098467) as applied to claim 11 above and further in view of Yu et al. (US 20230008349).
Regarding claim 16, Wang et al. in combination with Hsu et al. and Fujiwara et al. teach the limitations with respect to claim 14.
However, Wang et al. in combination with Hsu et al. and Fujiwara et al. are silent with respect to further comprising:
forming a dummy transistor in the device layer, wherein a gate structure of the dummy transistor is spaced apart from and aligned with one of the four gate structures that serves as a gate structure of the first pass-gate transistor of the first SRAM cell from the top view, and wherein the first power rail is electrically couple to the gate structure of the dummy transistor.
Yu et al. teach forming a dummy transistor in the device layer, wherein a gate structure of the dummy transistor is spaced apart from and aligned with one of the four gate structures that serves as a gate structure of the first pass-gate transistor of the first SRAM cell from the top view, and wherein the first power rail is electrically couple to the gate structure of the dummy transistor [see Fig. 6, dummy PMOS transistor having a dummy gate 320 configured to be coupled to the power voltage VDD through gate via 322 to M0 layer track 220, para. 81].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yu et al. to the teaching of Wang et al. in combination with Hsu et al. and Fujiwara et al. such that incorporating Yu et al.’s dummy transistor feature into SRAM layout of Wang et al. in combination with Hsu et al. and Fujiwara et al. to improve electrical stability and maintain layout regularity in dense SRAM design without changing the fundamental SRAM electrical operation.
Response to Arguments
Applicant’s arguments with respect to claims 1-17 and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY H LUONG/Examiner, Art Unit 2825
/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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