DETAILED ACTION
This action is responsive to the following communications: the Response to Election/Restriction filed on November 10, 2025 and the Information Disclosure Statement filed on January 31, 2024.
Claims 1-17 and 21-23 are pending. Claim 18-20 are canceled. Claims 21-23 are added. Claims 1, 11 and 21 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on January 31, 2024. This IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-17) in the reply filed on November 10, 2025 is acknowledged. Claims 18-20 were cancelled by applicant and thus are not under consideration.
Drawings
The drawings are objected to because all of the Figures filed on January 31, 2024 are degraded, showing dotted lines and dotted lettering and numbering, which may indicate applicant submitted Figures that were in greyscale. Applicant is reminded that solid lines used in the Drawings must be uniformly thick, black, and solid and the words and labels in the Drawings must be plain and legible. MPEP 608.02(f)(V).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 15 is objected to because of the following informalities:
Claim 15 has typographical informalities.
Claim 15 recites “a first pass-up transistor” and “a second pass---up transistor.” For reasons that follow, it appears applicant intended these transistors to be the pull-up transistors.
Additionally, the first power rail is recited as “electrically couple[d] to [a] sharing source/drain (sic) region between the first gate structure of the first pass-up (sic) transistor and a second gate structure of the second pass-up (sic) transistor.” It seems applicant means the first power rails is connected to the source regions of the first and second pull-up transistors. This assumption is based on the originally filed Specification, paragraph 51, which explains “[T]he high power rails Vdd are located at cell boundaries and shared with one of adjacent cells, and electrically connected to source node of transistors PU1 and PU2.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “the first contact has a first dimension extending in the first direction, and a second dimension extending in the first direction, and the first dimension is greater than the second dimension”. The claim is internally inconsistent and ambiguous because it requires both the “first dimension” and the “second dimension” to extend in the same “first direction”, while also requiring that one dimension be greater than the other. It is unclear how two different dimensions are be measured in the same direction and what physical relationship is intended.
Accordingly, claim 6 fails to particularly point out distinctly claim the invention; therefore, claim 6 is indefinite under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-9 and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 20210305262).
Regarding independent claim 1, Wang et al. disclose a method, comprising:
forming a static random access memory (SRAM) array in a device layer, wherein the SRAM array comprises a first SRAM cell and a second SRAM cell adjacent to the first SRAM cell, and from a top view, the first and second SRAM cells are arranged in a first direction [see Fig. 2 as well as Fig. 4A, FIG. 2 illustrates memory cells laid out in a set of columns 202a, 202b, 202c, 202d, and rows 204a, 204b, 204c, 204d, para. 26. Fig. 4A illustrates layout of memory cells 401, 403 for an SRAM memory cell layout. It is noted that cell 403 is symmetric (reflected across y-axis) to cell 401, para. 37];
forming a first word line over a front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37] and extending across the first and second SRAM cells in the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26], wherein the first word line is electrically coupled to the first SRAM cell [see Fig. 2, memory cell 210 is positioned within column 202b and row 204a, para. 27. The memory cell 210 connects only to one of the two word lines 208a, 208b. Specifically, memory cell 210 connects to word line 208a, para. 28]; and
forming a bit line and a bit line bar over a back-side of the device layer, wherein the first and second SRAM cells share the bit line and the bit line bar [FIG. 4B illustrates the layout of the memory cells 401, 403 with respect to the backside of the substrate. Both of the BL and BLB lines on both sides of the memory cells 401, 403 are shared with adjacent memory cells in adjacent columns, para. 38].
Regarding claim 2, Wang et al. disclose further comprising:
forming a second word lines over the front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37] and extending across the first and second SRAM cells in the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26], wherein the second word line is electrically coupled to the second SRAM cell [see Fig. 2, the adjacent memory cells within row 202a connect to word line 208b and do not connect with word line 208a, para. 28].
Regarding claim 3, Wang et al. disclose wherein the bit line and the bit line bar extend along a second direction in perpendicular to the first direction [see Fig. 2, bit lines (including bit lines 206a, 206b) are shown in dotted boxes extending parallel to the columns 202a, 202b, 202c, 202d while word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d, para. 26].
Regarding claim 4, Wang et al. disclose wherein from the top view, a first dimension of the first SRAM cell measured in the first direction is less than a second dimension of the first SRAM cell measured in a second direction perpendicular to the first direction [Wang et al. disclose the bit lines are at least approximately 50% wider than the word lines. The width may be measured in the top view, para. 26. Moreover, Wang et al. also disclose word lines extend along a first direction while the bit line and the bit line bar extend along a second direction, thus a person of ordinary skill in the art would have found it obvious that a first dimension of the first SRAM cell measured in the first direction is less than a second dimension of the first SRAM cell measured in a second direction perpendicular to the first direction].
Regarding claim 8, Wang et al. disclose further comprising:
forming a power rail over the back-side of the device layer, wherein the first and second SRAM cells share the power rail [see Fig. 4B, the power line Vdd is formed on the backside of the substrate and shared between adjacent cells 401 and 403, para. 37-38].
Regarding claim 9, Wang et al. disclose wherein from the top view, the power rail extends in parallel with the bit line and the bit line bar [see Fig. 4B, the power line Vdd is parallel with the bit lines BL and BLB, para. 37-38].
Regarding independent claim 21, Wang et al. disclose a method, comprising:
forming a first word line over a front-side of a device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37], wherein the device layer comprises a first static random access memory (SRAM) cell and a second SRAM cell arranged along a first direction from a top view [see Fig. 2 as well as Fig. 4A, FIG. 2 illustrates memory cells laid out in a set of columns 202a, 202b, 202c, 202d, and rows 204a, 204b, 204c, 204d, para. 26. Fig. 4A illustrates layout of memory cells 401, 403 for an SRAM memory cell layout. It is noted that cell 403 is symmetric (reflected across y-axis) to cell 401, para. 37], and wherein the first word line extends along the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26] and electrically coupled to the first SRAM cell [see Fig. 2, memory cell 210 is positioned within column 202b and row 204a, para. 27. The memory cell 210 connects only to one of the two word lines 208a, 208b. Specifically, memory cell 210 connects to word line 208a, para. 28];
forming a second word line over the front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37], wherein the second word line extends along the first direction [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26] and electrically coupled to the second SRAM cell [see Fig. 2, the adjacent memory cells within row 202a connect to word line 208b and do not connect with word line 208a, para. 28];
forming a bit line over a back-side of the device layer [FIG. 4B illustrates the layout of the memory cells 401, 403 with respect to the backside of the substrate. Both of the BL and BLB lines on both sides of the memory cells 401, 403 are shared with adjacent memory cells in adjacent columns, para. 38], wherein the bit line extends along a second direction and is electrically coupled to the first and second SRAM cells, and the second direction is different from the first direction in the top view [see Fig. 2, bit lines 206a is shown in dotted boxes extending parallel to the columns 202a, 202b, 202c, 202d. Connections from bit line 206a to a particular memory cell columns 202a, 202b are shown with filled in dots, para. 26]; and
forming a bit line bar over the back-side of the device layer and at a same level height as the bit line, wherein the bit line bar is electrically coupled to the first and second SRAM cells [FIG. 4B illustrates the layout of the memory cells 401, 403 with respect to the backside of the substrate. Both of the BL and BLB lines on both sides of the memory cells 401, 403 are shared with adjacent memory cells in adjacent columns, para. 38].
Regarding claim 22, Wang et al. disclose further comprising:
forming a power rail over the back-side of the device layer and at the same level height as the bit line and the bit line bar, wherein the power rail is electrically coupled to the first and second SRAM cells, and from the top view, the power rail is between the bit line and the bit line bar [see Fig. 4B, the power line Vdd is formed on the backside of the substrate and shared between adjacent cells 401 and 403. The power line Vdd is between the bit line BL and the bit line bar BLB, para. 37-38].
Regarding claim 23, Wang et al. disclose further comprising:
forming a first power rail over the front-side of the device layer and electrically couple to the first SRAM cell [Fig. 4A illustrates the via connections 402 from the active regions to the Vss power lines formed on the frontside of the substrate. The Vss lines may be shared with adjacent memory cells, para. 37]; and
forming a second power rail over the front-side of the device layer and electrically coupled to the second SRAM cell, wherein the first and second power rails extend along the second direction [Fig. 4A illustrates the via connections 402 from the active regions to the Vss power lines formed on the frontside of the substrate. The Vss lines may be shared with adjacent memory cells, para. 37], and form the top view, the bit line and the bit line bar are between the first and second power rails [see Fig. 5B, para. 43].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7, 10-12, 14-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210305262) in view of Fujiwara et al. (US 20210098467).
Regarding claims 5, Wang et al. teach the limitations with respect to claim 1.
Furthermore, Wang et al. disclose the first and second SRAM cells each comprises first and second pass-gate transistors [see Fig. 1: PG1, PG2, para. 22 and 24] and method further comprises:
forming a first contact over the back-side of the device layer prior to the step of forming the bit line and the bit line bar [Fig. 4B: contacts 404, para. 38].
However, Wang et al. are silent with respect to wherein the first contact extends from a first source/drain region of the first pass-gate transistor of the first SRAM cell to a second source/drain region of the first pass-gate transistor of the second SRAM cell, and the bit line is electrically coupled to the first and second SRAM cells through the first contact.
Fujiwara et al. teach a first contact extends from a first source/drain region of the first pass-gate transistor of the first SRAM cell to a second source/drain region of the first pass-gate transistor of the second SRAM cell, and the bit line is electrically coupled to the first and second SRAM cells through the first contact [see Fig. 7, the connection of the bit cells 410 and 450 to the bit line BL are made by the via 492, which is connected to the shared S/D contact 402, which is a shared S/D contact of both the pass gate PG0 transistors of both the bit cells 410 and 450, para. 50].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Fujiwara et al. to the teaching of Wang et al. such that incorporating shared source/drain contact and via connection scheme as taught by Fujiwara et al. into Wang et al.’s shared bit line SRAM architecture to achieve predictable benefits – fewer contacts/vias per bit cell, reducing routing congestion and improving parasitic performance.
Regarding claims 7, Wang et al. in combination with Fujiwara et al. teach the limitations with respect to claim 5.
Furthermore, Fujiwara et al. disclose further comprising:
forming a second contact over the back-side of the device layer prior to the step of forming the bit line and the bit line bar, wherein the second contact extends from a third source/drain region of the second pass-gate transistor of the first SRAM cell to a fourth source/drain region of the second pass-gate transistor of the second SRAM cell, and the bit line bar is electrically coupled to the first and second SRAM cells through the second contact [see Fig. 7, the connection of the bit cells 410 and 450 to the complementary bit line BLB are made by the via 496, which is connected to the shared S/D contact 406, which is a shared S/D contact of both the pass gate PG1 transistors of both the bit cells 410 and 45, para. 50].
Regarding claims 10, Wang et al. teach the limitations with respect to claim 8.
Furthermore, Wang et al. disclose wherein the first and second SRAM cells each comprises first and second pull-down transistors [see Fig. 1: PD1, PD2, para. 22-24], and the method further comprises:
forming a contact over the back-side of the device layer prior to the step of forming the power rail [Fig. 4B: contacts 404, para. 38].
However, Wang et al. are silent with respect to wherein the contact extends from a first source/drain region between the first and second pull-down transistors of the first SRAM cell to a second source/drain region between the first and second pull-down transistors of the second SRAM cell, and the power rail is electrically coupled to the first and second SRAM cells through the contact [see Fig. 7, the S/D contact 404 extends from the fin 414 in the negative Y-axis direction and is connected to the fin 454 between the poly 464 and the poly 466, and is connected to VSS in the M1 metal layer by the via 494. The first bit cell 410 and the second bit cell “share” the S/D contact 404. The PD0 and PD1 transistors share the S/D contact 404 and are thereby connected to the reference voltage VSS in the M1 layer, e.g. ground, para. 42].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Fujiwara et al. to the teaching of Wang et al. such that incorporating shared source/drain contact and via connection scheme as taught by Fujiwara et al. into Wang et al.’s shared bit line SRAM architecture to achieve predictable benefits – fewer contacts/vias per bit cell, reducing routing congestion and improving parasitic performance.
Regarding independent claim 11, Wang et al. disclose a method, comprising:
forming a first static random access memory (SRAM) cell and a second SRAM cell in a device layer [see Fig. 2 as well as Fig. 4A, FIG. 2 illustrates memory cells laid out in a set of columns 202a, 202b, 202c, 202d, and rows 204a, 204b, 204c, 204d, para. 26. Fig. 4A illustrates layout of memory cells 401, 403 for an SRAM memory cell layout. It is noted that cell 403 is symmetric (reflected across y-axis) to cell 401, para. 37], wherein the first and second SRAM cell each comprises a first pass-gate transistor and a second pass-gate transistor [see Fig. 1: PG1, PG2, para. 22 and 24];
forming a first back-side contact [Fig. 4B: contacts 404, para. 38];
forming a second back-side contact [Fig. 4B: contacts 404, para. 38];
forming a first back-side via over the first back-side contact [see Fig. 5B, the semiconductor material of the active regions 504a, 504b, 504c at this cross-section have been replaced with conductive materials to allow contact to the associated transistor terminal, para. 43];
forming a second back-side via over the second back-side contact [see Fig. 5B, the semiconductor material of the active regions 504a, 504b, 504c at this cross-section have been replaced with conductive materials to allow contact to the associated transistor terminal, para. 43];
forming a bit line over the first back-side via [see Fig. 5B, there is a via 504b connecting the source/drain feature (of active region 502b) to the bit line BL, para. 43].
However, Wang et al. are silent with respect to forming a first back-side contact extending from a first source/drain region of the first pass-gate transistor of the first SRAM cell to a second source/drain region of the first pass-gate transistor of the second SRAM cell;
forming a second back-side contact extending from a third source/drain region of the second pass-gate transistor of the first SRAM cell to a fourth source/drain region of the second pass-gate transistor of the second SRAM cell; and
forming a bit line bar over the second back-side via.
Fujiwara et al. teach forming a first back-side contact extending from a first source/drain region of the first pass-gate transistor of the first SRAM cell to a second source/drain region of the first pass-gate transistor of the second SRAM cell [see Fig. 7, the connection of the bit cells 410 and 450 to the bit line BL are made by the via 492, which is connected to the shared S/D contact 402, which is a shared S/D contact of both the pass gate PG0 transistors of both the bit cells 410 and 450, para. 50];
forming a second back-side contact extending from a third source/drain region of the second pass-gate transistor of the first SRAM cell to a fourth source/drain region of the second pass-gate transistor of the second SRAM cell [see Fig. 7, the connection of the bit cells 410 and 450 to the complementary bit line BLB are made by the via 496, which is connected to the shared S/D contact 406, which is a shared S/D contact of both the pass gate PG1 transistors of both the bit cells 410 and 45, para. 50];
forming a first back-side via over the first back-side contact [see Fig. 7, the S/D contact 402 is connected to the bit line BL in the M1 metal layer by the via 492, para. 37];
forming a second back-side via over the second back-side contact [see Fig. 7, the S/D contact 406 is connected to the complementary bit line BLB in the M1 metal layer by the via 496, para. 37];
forming a bit line over the first back-side via [see Fig. 7, the connection of the bit cells 410 and 450 to the bit line BL are made by the via 492, para. 50]; and
forming a bit line bar over the second back-side via [see Fig. 7, the connection of the bit cells 410 and 450 to the complementary bit line BLB are made by the via 496, para. 50].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Fujiwara et al. to the teaching of Wang et al. such that incorporating shared source/drain contacts and vias connection scheme as taught by Fujiwara et al. into Wang et al.’s shared bit line SRAM architecture to achieve predictable benefits – fewer contacts/vias per bit cell, reducing routing congestion and improving parasitic performance.
Regarding claims 12, Wang et al. in combination with Fujiwara et al. teach the limitations with respect to claim 11.
Furthermore, Wang et al. disclose further comprising:
forming a first word lines over a front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37] and extending across the first and second SRAM cells [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26]; and
forming a second word lines over the front-side of the device layer [Fig. 4A illustrates the via connections 304 that connect the active regions (e.g., source/drain features) to the word lines, para. 37] and extending across the first and second SRAM cells [see Fig. 2, word lines (including word lines 208a, 208b) are shown in dotted boxes extending parallel to the rows 204a, 204b, 204c, 204d. Connections from bit lines to a particular memory cell are shown with filled in dots, para. 26], wherein the first word line is electrically coupled to the first SRAM cell [see Fig. 2, memory cell 210 is positioned within column 202b and row 204a, para. 27. The memory cell 210 connects only to one of the two word lines 208a, 208b. Specifically, memory cell 210 connects to word line 208a, para. 28], and the second word line is electrically coupled to the second SRAM cell [see Fig. 2, the adjacent memory cells within row 202a connect to word line 208b and do not connect with word line 208a, para. 28].
Regarding claims 14, Wang et al. in combination with Fujiwara et al. teach the limitations with respect to claim 11.
Furthermore, Wang et al. disclose further comprising:
forming a first power rail over a front-side of the device layer and extending along a cell boundary of the first SRAM cell [see Fig. 4A, the Vss lines are formed on the frontside of the substrate and shared with adjacent memory cells, para. 37].
Regarding claims 15, Wang et al. in combination with Fujiwara et al. teach the limitations with respect to claim 14.
Furthermore, Fujiwara et al. disclose wherein the first SRAM cell comprises a first pass-up transistor and a second pass-up transistor, and the first power rail is electrically couple to a sharing source/drain region between a first gate structure of the first pass-up transistor and a second gate structure of the second pass-up transistor [see Fig. 7, power is supplied on the VDD lines in the first metal layer M1, and is connected to the S/D contact 434 of both PU0 and PU1 of the first bit cell 410 by the via 441, para. 35].
Regarding claims 17, Wang et al. in combination with Fujiwara et al. teach the limitations with respect to claim 14.
Furthermore, Fujiwara et al. disclose further comprising:
forming a second power rail over a back-side of the device layer, wherein the second power rail is electrically couple to the first power rail and overlaps with the first power rail [see Fig. 7, the S/D contacts 434 and 474 are connected to a VDD line in the M1 layer by the vias 441 and 481, and the S/D contact 404 is connected to a VSS line in the M1 layer by the via 494, para. 60].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210305262) in view of Fujiwara et al. (US 20210098467) as applied to claim 11 above and further in view of Yang et al. (US 20220319583).
Regarding claim 13, Wang et al. in combination with Fujiwara et al. teach the limitations with respect to claim 11.
However, Wang et al. in combination with Fujiwara et al. are silent with respect to further comprising:
forming a dielectric gate in the device layer, wherein the dielectric gate is in contact with and aligned with a gate structure of the first pass-gate transistor of the first SRAM cell from a top view.
Yang et al. teach forming a dielectric gate in the device layer, wherein the dielectric gate is in contact with and aligned with a gate structure of the first pass-gate transistor of the first SRAM cell from a top view [see Fig. 4, the first metal gate cut feature 420A and the second metal gate cut feature 420B includes one or more dielectric material filled into a metal gate cut trench that completely severs the respective metal gate stack (406-1 or 406-2) that formed over the fin/fins active regions used for SRAM transistors, para. 30.
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yang et al. to the teaching of Wang et al. in combination with Fujiwara et al. such that incorporating Yang et al.’s dielectric gate feature into SRAM layout of Wang et al. in combination with Fujiwara et al. to enhance isolation and process robustness without changing the fundamental SRAM electrical operation.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210305262) in view of Fujiwara et al. (US 20210098467) as applied to claim 11 above and further in view of Yu et al. (US 20230008349).
Regarding claim 16, Wang et al. in combination with Fujiwara et al. teach the limitations with respect to claim 14.
However, Wang et al. in combination with Fujiwara et al. are silent with respect to further comprising:
forming a dummy transistor in the device layer, wherein a gate structure of the dummy transistor is spaced apart from and aligned with a gate structure of the first pass-gate transistor of the first SRAM cell from a top view, wherein the first power rail is electrically couple to the gate structure of the dummy transistor.
Yu et al. teach forming a dummy transistor in the device layer, wherein a gate structure of the dummy transistor is spaced apart from and aligned with a gate structure of the first pass-gate transistor of the first SRAM cell from a top view, wherein the first power rail is electrically couple to the gate structure of the dummy transistor [see Fig. 6, dummy PMOS transistor having a dummy gate 320 configured to be coupled to the power voltage VDD through gate via 322 to M0 layer track 220, para. 81].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Yu et al. to the teaching of Wang et al. in combination with Fujiwara et al. such that incorporating Yu et al.’s dummy transistor feature into SRAM layout of Wang et al. in combination with Fujiwara et al. to improve electrical stability and maintain layout regularity in dense SRAM design without changing the fundamental SRAM electrical operation.
Conclusion
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825