DETAILED ACTION
Election/Restrictions
Applicant’s election of Species 2, figures 3A/3B, in the reply filed on 5/19/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US 10,217,720, in view of Shih et al., US 12,354,965.
Regarding claim 1, Wang (see figure 1-6 & marked up figure 4-6 below) teaches a semiconductor device, comprising:
a first integrated circuit 126, comprising a first interconnect structure 102a, a first passivation layer 102 (column 6, lines 6-9 says BOEL stacks & column 3, lines 58-61 states the BOEL stack has a last layer of passivation) and a first conductive connector 130 electrically connected to the first interconnect structure 102a and disposed on the first passivation layer 102;
a bridge die 103, comprising a second interconnect structure 102b, a second passivation layer (column 3, lines 58-61 states the BOEL stack has a last layer of passivation) and a second conductive connector 116 electrically connected to the second interconnect structure 102b; and
a redistribution layer (RDL) structure 201, disposed between and electrically connected to the first integrated circuit 126 and the bridge die 103, wherein the first passivation layer 102 (column 6, lines 6-9 says BOEL stacks & column 3, lines 58-61 states the BOEL stack has a last layer of passivation) is in direct contact with the first conductive connector 130, the first conductive connector 130 is in direct contact with the RDL structure 201, and the first passivation layer 102 (column 6, lines 6-9 says BOEL stacks & column 3, lines 58-61 states the BOEL stack has a last layer of passivation) is a single layer (column 3, lines 58-61 states the passivation has one or more layers).
Wang fails to teach the passivation layer is made of a first inorganic material.
Shih (column 12, line 66-column 13, line 1) teaches a passivation layer comprising silicon oxide or silicon nitride.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the inorganic materials of Shih in the invention of Wang because Shih teaches conventionally known and used inorganic passivation materials. The use of conventional materials to perform their known functions is obvious (MPEP 2144.07).
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With respect to claim 2, wherein the first integrated circuit 126 comprises an active device (column 6, lines 3-4), and the bridge die is free of active devices (column 3, lines 32-34).
As to claim 3, Wang (figures 1-6 & marked up figure 4-6 above) teaches the first interconnect structure 102a comprises a plurality of first dielectric layers (column 4, line 1 calls it a BOEL stack therefore it has a plurality of dielectric layers), the second interconnect structure 102b comprises a plurality of second dielectric layers (column 6, line 8 calls it a BOEL stack therefore it has a plurality of dielectric layers), and though Wang fails to teach a dielectric constant of each of the first dielectric layers is lower than a dielectric constant of each of the second dielectric layers, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the relative dielectric constant through routine experimentation (MPEP 2144.05).
In re claim 4, Wang (figures 1-6 & marked up figure 4-6 above) teaches the second passivation layer (column 3, lines 58-61 states the BOEL stack has a last layer of passivation) is in direct contact with the second conductive connector 116, the second conductive connector 116 is in direct contact with the RDL structure 201, and the second passivation layer is a single layer (column 4, lines 58-61 states the passivation has one or more layers), and Shih (column 12, line 66-column 13, line 1) teaches the passivation layer includes a second inorganic material.
Concerning claim 5, Wang (column 10, lines 6-24) teaches the RDL structure 201 comprises a plurality of first conductive patterns stacked and overlapped with one another along a stacking direction of the first integrated circuit 126 and the bridge die 103.
Pertaining to claim 6, Shih (column 12, line 66-column 13, line 1) teaches the first inorganic material of the first passivation layer comprises silicon oxide, silicon nitride or a combination thereof.
Claim(s) 7-12[ is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US 10,217,720, in view of Peng et al., US 2024/0387347.
In claim 7, Wang (figures 1-6 & marked up figure 4-6 above) teaches a semiconductor device, comprising:
a first integrated circuit 126, comprising a first active device (column 6, lines 3-4), a first conductive pad (under 116), a first passivation layer (column 6, lines 6-9 says BOEL stacks 102 & column 3, lines 58-61 states the BOEL stack has a last layer of passivation), a first conductive connector 116 on the first passivation layer (column 6, lines 6-9 says BOEL stacks 102 & column 3, lines 58-61 states the BOEL stack has a last layer of passivation);
a bridge die 103 free of active devices (column 3, lines 32-34) electrically connected to the first integrated circuit 126; and
a RDL structure 201, disposed between and electrically connected to the first integrated circuit 126 and the bridge die 103, the RDL structure 201 comprising a plurality of second dielectric layers and a plurality of conductive patterns in the second dielectric layers (column 10, lines 6-24), wherein the first passivation layer (column 6, lines 6-9 says BOEL stacks 102 & column 3, lines 58-61 states the BOEL stack has a last layer of passivation) is in direct contact with the first conductive pad (under 116),
Wang fails to teach a first dielectric layer surrounding the first conductive connector 116; the first passivation is in direct contact with the first dielectric layer; the first dielectric layer is in direct contact with one of the second dielectric layers; and a hardness of the first passivation layer is larger than a hardness of the first dielectric layer.
Peng (figure 1F) teaches a first dielectric layer 146 surrounding the first conductive connector (solder between 134 & 124M); the first passivation 132 is in direct contact with the first dielectric layer 146; the first dielectric layer 146 is in direct contact with one of the second dielectric layers (in 124); and a hardness of the first passivation layer (paragraph 0042 states passivation 116 can be SiO or SiN) is larger than a hardness of the first dielectric layer paragraph 0044 states it is epoxy, polyimide, PBO etc).
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the first dielectric of Peng in the invention of Wang because skilled artisans know it protects the first conductive connector from the environment and also reinforces the connection between dies 128 and the RDL 124.
Regarding claim 8, Wang teaches the first passivation layer (column 6, lines 6-9 says BOEL stacks 102 & column 3, lines 58-61 states the BOEL stack has a last layer of passivation) is a single layer (column 3, lines 58-61) and Peng (paragraph 0042) teaches the passivation layers can be made of an inorganic layer.
With respect to claim 9, Peng (paragraph 0042) teaches a material of the first passivation layer 132 comprises silicon oxide, silicon nitride or a combination thereof.
As to claim 10, Peng (figure 1F) teaches the first passivation layer 132 is in direct contact with the first conductive connector (solder between 134 & 124M), and the first conductive connector (solder between 134 & 124M) is in direct contact with one of the conductive patterns 134.
In re claim 11, wherein a surface of the first dielectric layer 146 facing the RDL structure 124 is substantially coplanar with a surface of the first conductive connector (solder between 134 & 124M).
Concerning claim 12, Peng teaches the hardness of the first passivation layer (paragraph 0042 states passivation 116 can be SiO or SiN) is larger than a hardness of the one of the second dielectric layers (column 10, lines 1-2 teaches polyimide).
Claim(s) 13-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al., US 10,217,720, in view of Peng et al., US 2024/0387347.
Pertaining to claim 13, Wang (figures 1-6 & marked up figure 4-6 above) teaches a semiconductor device, comprising:
a first integrated circuit 126, comprising a first conductive pad (under 116), a first passivation layer (column 6, lines 6-9 says BOEL stacks 102 & column 3, lines 58-61 states the BOEL stack has a last layer of passivation) covering the first conductive pad (under 116), a first conductive connector 116 disposed on the first passivation layer, wherein the first passivation layer is a single layer (column 3, lines 58-61);
a second integrated circuit 127;
a bridge die 103 free of active devices (column 3, lines 32-34), comprising a second conductive connector 116; and
a RDL structure 201 between the first integrated circuit 126 and the bridge die 103 and between the second integrated circuit 127 and the bridge die 103, the RDL 201 comprising a plurality of conductive patterns stacked between the first conductive connector and the second conductive connector (column 10, lines 6-24), wherein the bridge die 103 electrically connects the first integrated circuit 126 and the second integrated circuit 127 through the conductive patterns.
Wang fails to teach a first dielectric layer surrounding the first conductive connector; and the first passivation layer is in direct contact with the first conductive pad, the first conductive connector and the first dielectric layer.
Peng (figure 1F) teaches a first dielectric layer 136 surrounding the first conductive connector (134 & solder below); and the first passivation layer 132 is in direct contact with the first conductive pad 130, the first conductive connector (134 and solder below it) and the first dielectric layer 146.
It would have been obvious to one of ordinary skill in the art at the time of the invention to use the first dielectric of Peng in the invention of Wang because skilled artisans know it protects the first conductive connector from the environment and also reinforces the connection between dies 128 and the RDL 124.
Peng (figure 1F) teaches a first dielectric layer surrounding the first conductive connector.
Also, Wang fails to teach the first passivation layer is an inorganic layer.
Peng (paragraph 0042 states passivation 116 can be SiO or SiN) teaches the first passivation layer 132 is an inorganic layer.
In claim 14, Peng (paragraph 0042 states passivation 116 can be SiO or SiN) teaches a material of the first passivation layer comprises silicon oxide, silicon nitride or a combination thereof.
Regarding claim 15, Wang (column 10, lines 6-24) teaches the conductive patterns are stacked along a first direction along which the first integrated circuit, the RDL structure and the bridge die are stacked.
With respect to claim 16, Wang (column 10, lines 6-24) teaches the conductive patterns comprise a plurality of conductive pads and a plurality of conductive vias, and the conductive pads and the conductive vias are alternately stacked and overlapped with one another along the first direction.
As to claim 17, though Wang fails to teach horizontal distances between the first conductive connector and the conductive patterns become increased as vertical distances between the first conductive connector and the conductive patterns increase, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the distance through routine experimentation (MPEP 2144.05).
In re claim 18, Wang (column 10, lines 6-24) teaches the conductive patterns comprise a first conductive via, a first conductive pad and a second conductive via, the first conductive via is physically connected to a first end of a first surface of the first conductive pad, the second conductive via is physically connected to a second end of a second surface of the first conductive pad, the first end is opposite to the second end, and the first surface is opposite to the second surface.
Concerning claim 19, Wang (column 10, lines 6-24) teaches the conductive patterns further comprise a third conductive via on the first conductive via, the first conductive pad and the second conductive via, and the third conductive via and the second conductive via are overlapped along a first direction along which the first integrated circuit, the RDL structure and the bridge die are stacked.
Pertaining to claim 21, Wang (figure 4-6) teaches the RDL structure 201 further comprises additional conductive patterns stacked between a third conductive connector of the first integrated circuit 126 and a fourth conductive connector of the second integrated circuit 127, and though Wang fails to teach horizontal distances between the third conductive connector and the additional conductive patterns are substantially constant as vertical distances between the third conductive connector and the additional conductive patterns increase, it would have been obvious to one ordinary skill in the art at the time of the invention to optimize the distances through routine experimentation (MPEP 2144.05).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art teach various aspects of the invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID A ZARNEKE whose telephone number is (571)272-1937. The examiner can normally be reached M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAVID A ZARNEKE/Primary Examiner, Art Unit 2891 7/2/26
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