Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Applicant’s IDS submitted on 6/2/25 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 8 and 19 both recite “hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2 with x ranging from 0 to 1), scandium-doped aluminum nitride (Al1-xScxN with x>0.3), titanates (BaTiO3), niobates (LiNbO3), or tantalates (NaTaO3)” the parentheticals make this phrase unclear because, the written text, such as titanates, is broader than the parenthetical that follows it BaTiO3; it is unclear if all titanates are claimed or only BaTaO3, the other parentheticals have the same issue. If the written compounds are included, they must match the parenthetical that follow the compound’s name. For purposes of examination these claims have been interpreted as claiming the written terms and not the chemical formulae.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 8, and 10-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Haratipour et al., US 20200395460 A1, hereafter Haratipour
Regarding independent claim 1, Haratipour discloses the following limitations:
A memory device (Figure 5, and [0010] which discloses it is a memory device and contains a capacitor over bit-line (COB) shown in any one of Figures 3-4), comprising:
a three-dimensional (3D) feature fabricated on a connection pad that comprises a conductive material (Haratipour, Figure 4A, opening in insulating material 310, formed on first interconnect 306/barrier layer 305, [0041] discloses 306 as one or more of Cu, Al, graphene, CNT, Au, Co, W, or TiN and 305 is disclosed as TiN);
a first electrode, wherein at least a portion of the first electrode is fabricated on a surface of the 3D feature (Haratipour, Figure 4A, first electrode material 301 is on the sides of the opening);
a ferroelectric layer fabricated on the first electrode, wherein the ferroelectric layer comprises a ferroelectric material (Haratipour, Figure 4A, ferroelectric material 303, disclosed as a ferroelectric material in [0040]); and
a second electrode fabricated on the ferroelectric layer (Haratipour, Figure 4A, second electrode 302).
Regarding claim 2, Haratipour discloses the following limitations:
The memory device of claim 1, wherein the 3D feature comprises at least one of a post, a fin, a trench, or a via (Haratipour, Figure 4A, opening is a trench in insulating material 310).
Regarding claim 3, Haratipour discloses the following limitations:
The memory device of claim 1, wherein the 3D feature comprises an opening fabricated in a dielectric layer (Haratipour, Figure 6L, opening is a trench via in insulating material 310, disclosed as SiO2 in [0063]), wherein the dielectric layer is fabricated on the connection pad (Haratipour, Figure 4A, insulating material 310 is formed on first interconnect 306).
Regarding claim 4, Haratipour discloses the following limitations:
The memory device of claim 3, wherein the 3D feature exposes at least a portion of the connection pad (Haratipour, Figure 4A, opening in insulating material 310 exposes first interconnect 306/barrier layer 305), and wherein at least a portion of the first electrode is fabricated on the exposed portion of the connection pad (Haratipour, Figure 4A, first electrode material 301).
Regarding claim 6, Haratipour discloses the following limitations:
The memory device of claim 1, wherein the connection pad is fabricated on a substrate (Haratipour, Figure 5, substrate 501, and capacitive structure 300, and [0046] discloses capacitive structure 400 can be substituted for capacitive structure 300, and 400 contains including first interconnect 306/Barrier layers 305), and wherein the 3D feature extends out of a two-dimensional plane of a top surface of the substrate (Haratipour, Figure 5, show the capacitor extending in the z-direction, out of the xy-plane).
Regarding claim 8, Haratipour discloses the following limitations:
The memory device of claim 1, wherein the ferroelectric material comprises a metal oxide, and wherein the metal oxide comprises at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2 with x ranging from 0 to 1), scandium-doped aluminum nitride (Al1-xScxN with x>0.3), titanates (BaTiO3), niobates (LiNbO3), or tantalates (NaTaO3) (Haratipour, [0040] discloses metal oxides for the ferroelectrics material such as LiNbO3, and BaTiO3).
Regarding claim 10, Haratipour discloses the following limitations:
The memory device of claim 1, wherein the first electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium, (Haratipour, Figure 4A, first interconnect 306/barrier layer 305, and [0041] discloses TiN for 305 and 306).
Regarding claim 11, Haratipour discloses the following limitations:
The memory device of claim 1, wherein the second electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium (Haratipour, second electrode 302, and [0038] discloses TaN, Ru, Ir, W, and TaN for 302).
Regarding independent claim 12, Haratipour discloses the following limitations:
A method for fabricating a memory device (Figure 5, and [0010] which discloses it is a memory device and contains a capacitor over bit-line (COB) shown in any one of Figures 3-4), the method comprising:
fabricating, on a connection pad comprising a conductive material (Figure 7A , electrode 306) a three-dimensional (3D) feature (Figure 7A, opening 621), wherein the connection pad is fabricated on a substrate (Figure 5, substrate 501);
fabricating a first electrode layer on the substrate, the connection pad, and the 3D feature (Figure 7A, first electrode material 301 is on the substrate Figure 5, 501 and electrode 306);
fabricating, on the first electrode layer, a ferroelectric layer comprising a ferroelectric material (Figure 7C, ferroelectric material 303 is formed on 301, and [0075] discloses that barrier 305 is optional); and
fabricating, on the ferroelectric layer, a second electrode layer (Figure 7D, second electrode 302 is formed on 303).
Regarding claim 13, Haratipour discloses the following limitations:
The method of claim 12, wherein the 3D feature comprises at least one of a post, a fin, a trench, or a via (Figure 7A, opening 621, and [0042] discloses the capacitor is a trench capacitor making 621 a trench).
Regarding claim 14, Haratipour discloses the following limitations:
The method of claim 12, wherein fabricating, on the connection pad, the 3D feature comprises fabricating a dielectric layer with an opening on the connection pad (Figure 7A, insulating material 310b, disclosed as SiO2 in [0063] with opening 621 are on 306).
Regarding claim 15, Haratipour discloses the following limitations:
The method of claim 14, wherein the 3D feature exposes at least a portion of the connection pad, and wherein at least a portion of the first electrode is fabricated on the exposed portion of the connection pad (Figure 7A, opening 621 in insulating material 310b, exposes electrode 306 and a portion of first electrode 301 is on the exposed portion, and [0075] discloses barrier layer 305 is optional).
Regarding claim 16, Haratipour discloses the following limitations:
The method of claim 15, wherein at least a portion of the first electrode is fabricated on a top surface of the dielectric layer and sidewall of the opening of the dielectric layer (Figure 7A, first electrode 301 is on top of insulating layer 310b (SiO2) and on the sidewalls of opening 621).
Regarding claim 17, Haratipour discloses the following limitations:
The method of claim 12, wherein the connection pad is fabricated on a substrate (Figure 5, capacitor 300 is on substrate 501), and wherein the 3D feature extends out of a two-dimensional plane of a top surface of the substrate (Figure 5, capacitor 300, and the trench it is in extend in the z-direction).
Regarding claim 18, Haratipour discloses the following limitations:
The method of claim 17, wherein at least a portion of the first electrode is fabricated on a top surface of the 3D feature and a top surface of the connection pad (Figure 7A, first electrode 301 is formed on top of oxide 310b and the top of electrode 306, and [0075] discloses barrier layer 305 is optional).
Regarding claim 19, Haratipour discloses the following limitations:
The method of claim 12, wherein the ferroelectric material comprises a metal oxide, and wherein the metal oxide comprises at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), zirconium-doped hafnium oxide (Hf1-xZrxO2 with x ranging from 0 to 1), scandium-doped aluminum nitride (Al1-xScxN with x>0.3), titanates (BaTiO3), niobates (LiNbO3), or tantalates (NaTaO3) (Haratipour, [0040] discloses metal oxides for the ferroelectrics material such as LiNbO3, and BaTiO3).
Regarding claim 20, Haratipour discloses the following limitations:
The method of claim 12, wherein the first electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium, and wherein the second electrode comprises at least one of tungsten, ruthenium, molybdenum, titanium nitride, tantalum nitride, tungsten nitride, platinum, palladium, or iridium (Haratipour, Figure 4A, first interconnect 306/barrier layer 305, and [0041] discloses TiN for 305 and 306).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour as applied under 35 U.S.C. §102, to claim 4 and 6 above, and further in view of Yamaguchi, US 20260068129 A1, hereafter Yamaguchi ‘129.
Regarding claim 5, Haratipour discloses the following limitations:
The memory device of claim 4, wherein at least a portion of the first electrode is fabricated on sidewalls of the 3D feature (Haratipour, Figure 4A, first electrode 301 is on the sidewalls of oxide 310).
Regarding claim 5, Haratipour fails to disclose the following limitations:
wherein at least a portion of the first electrode is fabricated on a top surface of the dielectric layer
Yamaguchi ‘129 discloses the following limitation:
wherein at least a portion of the first electrode is fabricated on a top surface of the dielectric layer (Yamaguchi ‘129, Figure 1B, conductor 115 is formed on the top surface of conductor 110 (a connection pad), the sidewalls of the opening portion 190 (a 3D feature) and on the top of insulator 180, discloses a silicon oxide in [0135]).
Haratipour discloses a memory device that includes everything claimed except it does not have the first electrode on the top surface of the dielectric layer in the finished device. Yamaguchi ‘129 teaches that when making capacitive devices the first (or lower) electrode can be deposited on the sidewalls and on top of the dielectric layer. It would have been obvious to one of ordinary skill in the art to substitute one known element (a first electrode that is on both the sidewalls and top surface of the dielectric) for another known equivalent (a first electrode that is on the sidewalls, but not on the top of the dielectric) resulting in the predictable result of forming a first electrode.
Regarding claim 7, Haratipour discloses the following limitations:
The memory device of claim 6, wherein at least a portion of the first electrode is fabricated on a top surface of the connection pad (Haratipour, Figure 4A, first electrode 301 is on first interconnect 306/barrier layer 305).
Haratipour fails to disclose the following limitations:
wherein at least a portion of the first electrode is fabricated on a top surface of the dielectric layer
Yamaguchi ‘129 discloses the following limitation:
wherein at least a portion of the first electrode is fabricated on a top surface of the dielectric layer (Yamaguchi ‘129, Figure 1B, conductor 115 is formed on the top surface of conductor 110 (a connection pad), the sidewalls of the opening portion 190 (a 3D feature) and on the top of insulator 180, discloses a silicon oxide in [0135]).
Haratipour discloses a memory device that includes everything claimed except it does not have the first electrode on the top surface of the dielectric layer in the finished device. Yamaguchi ‘129 teaches that when making capacitive devices the first (or lower) electrode can be deposited on the a connection pad, and on top of the dielectric layer. It would have been obvious to one of ordinary skill in the art to substitute one known element (a first electrode that is on both the connection pad and top surface of the dielectric) for another known equivalent (a first electrode that is on the connection pad, but not on the top of the dielectric) resulting in the predictable result of forming a first electrode.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Haratipour as applied under 35 U.S.C. §102, to claim 1 above, and further in view of Yamaguchi, US 20180337055 A1, hereafter Yamaguchi ‘055.
Regarding claim 9, Haratipour fails to discloses the following limitations:
The memory device of claim 1, wherein the ferroelectric material is interstitially doped with at least one interstitial dopant, and wherein the at least one interstitial dopant comprises at least one of H, N, C, B, or F.
Yamaguchi ‘055 discloses the following limitations:
wherein the ferroelectric material is interstitially doped with at least one interstitial dopant, and wherein the at least one interstitial dopant comprises at least one of H, N, C, B, or F (Yamaguchi ‘055, [0123]-[0126] discloses that the addition of impurities such as nitrogen, carbon or fluorine in in hafnium zirconium oxide or hafnium oxide films so that the films can exhibit ferroelectric properties).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Yamaguchi ‘055 to the device of Haratipour because Yamaguchi ‘055 teaches that doing so makes can make desirably thin films containing hafnium zirconium and oxygen that exhibit ferroelectric properties and that such thin films allow for the miniaturization of memory [0005].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al., US 20240381662 A1, discloses nitrogen doping of ferroelectric hafnium zirconium oxide improves (makes faster) read times in ferroelectric memories.
Isaka et al., WO 2024194728 A1, discloses the use of carbon as a dopant in HfZrOx ferroelectric material to control the polarization state in a ferroelectric memory device.
Lin et al., US 20200212055 A1 discloses a capacitor with a ferroelectric material for the dielectric where the first electrode is on the top of the insulating layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 10-2 ET.
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/LINDA J. FLECK/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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