DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9 and 11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on May 15, 2026.
Applicant's election with traverse of Species 2 and sub-Species A, claims 1-8, 10, 12-14, 18-22, and 25-30, in the reply filed on May 15, 2026 is acknowledged. The traversal is on the ground(s) that the Office Action does not provide a showing of serious burden and the election requirement fails to allege the existence of species that are independent and distinct. This is not found persuasive because MPEP 803.I. and MPEP 803.II. are met in the Office Action mailed March 18, 2026.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 11, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on June 12, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 10, 12-14, 18, 19, 21, 22, 25, 26, 29, and 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujii (US Pub 2016/0079442).
In re claim 1, Fujii discloses a power semiconductor device, comprising: a semiconductor structure comprising an active region (i.e. right-hand side in Figure 2 where the gate trench with adjacent emitter layers 4 is shown); a plurality of gates (i.e. 8, more gates are present since Figure 2 shows only a small portion of the active device region in Figure 1) that extend in a first direction (i.e. implicitly into the Figure plane of Figure 2) in or on the active region of the semiconductor structure; at least one integrated polysilicon device (i.e. 17, formed from same polysilicon layer 27 in the method of Figures 4-7) in or on a surface of the semiconductor structure adjacent the active region; and a gate connector (i.e. see Figure 2, n+ portion below gate wire 10 connecting to gate pad 11 according to paragraph 0037) electrically connecting the plurality of gates, wherein the gate connector is in or on the surface of the semiconductor structure between the at least one integrated polysilicon device and the plurality of gates, wherein the at least one integrated polysilicon device is electrically isolated from the gate connector devoid of an inter-polysilicon dielectric layer therebetween (i.e. the inter-polysilicon dielectric layer is understood to be a layer vertically separating polysilicon layers as shown in prior art Figure 8 of the instant application, there is no such layer in Figure 2 of Fujii).
In re claim 2, Fujii discloses wherein the at least one integrated polysilicon device (i.e. 17) does not overlap with the gate connector in a direction perpendicular to the surface of the semiconductor structure (i.e. implicitly by the fact that the same polysilicon layer is used).
In re claim 3, Fujii discloses wherein the at least one integrated polysilicon device comprises a surface that is coplanar with a surface of the gate connector (i.e. implicitly by the fact that the same polysilicon layer formed on the same insulating layer is used).
In re claim 4, Fujii discloses wherein the at least one integrated polysilicon device (i.e. 17) and the gate connector comprise portions of a same polysilicon layer (i.e. in this case, from polysilicon layer 27 in the method of Figures 4-7).
In re claim 5, Fujii discloses further comprising: an isolation layer (i.e. 16) on the surface of the semiconductor structure (i.e. see at least Figures 2 and 5), wherein the at least one integrated polysilicon device is on the isolation layer devoid of the inter-polysilicon dielectric layer therebetween (i.e. the inter-polysilicon dielectric layer is understood to be a layer vertically separating polysilicon layers as shown in prior art Figure 8 of the instant application, there is no such layer in Figure 2 of Fujii).
In re claim 6, Fujii discloses further comprising: an inter-metal dielectric layer on the gate connector and the at least one integrated polysilicon device; and respective conductive vias that extend through the inter-metal dielectric layer by a same depth to electrically contact the gate connector and the at least one integrated polysilicon device (i.e. see at least Figure 2).
In re claim 7, Fujii discloses wherein the plurality of gates respectively comprise first and second portions that extend in a first direction in respective gate trenches in the active region, and the gate connector has a different conductivity than the first portions (i.e. see at least Figures 4-7, the gate polysilicon 8 is formed earlier than the polysilicon 27 in Figure 5; for the gate polysilicon 8, in-situ doping at deposition is straight-forward and enables high doping levels, since doping by implantation would be more difficult in the trenches; in contrast, polysilicon layer 27 has to be initially formed without doping or at a low doping concentration to enable formation of a diode; therefore, a commonplace recess of the gate electrode in conjunction with a separate doping of the upper part forming the connection portions in each trench will normally result in an upper gate polysilicon portion that is less doped).
In re claim 8, Fujii discloses wherein the first portions of the plurality of gates comprise a greater dopant concentration than the second portions, and the gate connector comprises a same dopant concentration as the second portions of the plurality of gates (i.e. see at least Figures 4-7, the gate polysilicon 8 is formed earlier than the polysilicon 27 in Figure 5; for the gate polysilicon 8, in-situ doping at deposition is straight-forward and enables high doping levels, since doping by implantation would be more difficult in the trenches; in contrast, polysilicon layer 27 has to be initially formed without doping or at a low doping concentration to enable formation of a diode; therefore, a commonplace recess of the gate electrode in conjunction with a separate doping of the upper part forming the connection portions in each trench will normally result in an upper gate polysilicon portion that is less doped).
In re claim 10, Fujii discloses wherein the plurality of gates extend in respective gate trenches in the active region, and wherein the at least one integrated polysilicon device comprises a planar surface on the surface of the semiconductor structure adjacent the active region (i.e. see at least Figures 2, 4-7).
In re claim 12, Fujii discloses a power semiconductor device, comprising: a semiconductor structure comprising an active region (i.e. right-hand side in Figure 2 where the gate trench with adjacent emitter layers 4 is shown); a plurality of gates (i.e. 8, more gates are present since Figure 2 shows only a small portion of the active device region in Figure 1) that extend in a first direction in or on the active region of the semiconductor structure; a gate connector (i.e. see Figure 2, n+ portion below gate wire 10 connecting to gate pad 11 according to paragraph 0037) electrically connecting the plurality of gates; and at least one integrated polysilicon device (i.e. 17, formed from same polysilicon layer 27 in the method of Figures 4-7) in or on the semiconductor structure adjacent the gate connector, wherein the at least one integrated polysilicon device and the gate connector comprise respective surfaces that are coplanar (i.e. implicitly by the fact that the same polysilicon layer formed on the same insulating layer is used).
In re claim 13, Fujii discloses wherein the respective surfaces of the at least one integrated polysilicon device and the gate connector comprise portions of a same polysilicon layer (i.e. in this case, from polysilicon layer 27 in the method of Figures 4-7).
In re claim 14, Fujii discloses wherein the at least one integrated polysilicon device is electrically isolated from the gate connector devoid of an inter- polysilicon dielectric layer therebetween (i.e. the inter-polysilicon dielectric layer is understood to be a layer vertically separating polysilicon layers as shown in prior art Figure 8 of the instant application, there is no such layer in Figure 2 of Fujii).
In re claim 18, Fujii discloses a power semiconductor device, comprising: a semiconductor structure comprising an active region (i.e. right-hand side in Figure 2 where the gate trench with adjacent emitter layers 4 is shown); a plurality of gates (i.e. 8, more gates are present since Figure 2 shows only a small portion of the active device region in Figure 1) that extend in a first direction in or on the active region of the semiconductor structure; a gate connector (i.e. see Figure 2, n+ portion below gate wire 10 connecting to gate pad 11 according to paragraph 0037) electrically connecting the plurality of gates; at least one integrated polysilicon device (i.e. 17, formed from same polysilicon layer 27 in the method of Figures 4-7) in or on the semiconductor structure adjacent the gate connector; an inter-metal dielectric layer on the gate connector and the at least one integrated polysilicon device (i.e. see at least Figure 2); and respective conductive vias that extend through the inter-metal dielectric layer by a same depth to electrically contact the gate connector and the at least one integrated polysilicon device (i.e. see at least Figure 2).
In re claim 19, Fujii discloses wherein the at least one integrated polysilicon device comprises a surface that is coplanar with a surface of the gate connector (i.e. implicitly by the fact that the same polysilicon layer formed on the same insulating layer is used).
In re claim 21, Fujii discloses wherein the at least one integrated polysilicon device and the gate connector comprise portions of a same polysilicon layer (i.e. in this case, from polysilicon layer 27 in the method of Figures 4-7).
In re claim 22, Fujii discloses wherein the at least one integrated polysilicon device is electrically isolated from the gate connector devoid of an inter-polysilicon dielectric layer therebetween i.e. the inter-polysilicon dielectric layer is understood to be a layer vertically separating polysilicon layers as shown in prior art Figure 8 of the instant application, there is no such layer in Figure 2 of Fujii).
In re claim 25, Fujii discloses a power semiconductor device, comprising: a semiconductor structure comprising an active region (i.e. right-hand side in Figure 2 where the gate trench with adjacent emitter layers 4 is shown); a plurality of gates (i.e. 8, more gates are present since Figure 2 shows only a small portion of the active device region in Figure 1) that extend in a first direction in respective trenches in the active region of the semiconductor structure; at least one integrated polysilicon device (i.e. 17, formed from same polysilicon layer 27 in the method of Figures 4-7) in or on the semiconductor structure adjacent the plurality of gates; and a gate connector (i.e. see Figure 2, n+ portion below gate wire 10 connecting to gate pad 11 according to paragraph 0037) electrically connecting the plurality of gates, wherein the gate connector is in or on the semiconductor structure between the at least one integrated polysilicon device and the plurality of gates, wherein the plurality of gates respectively comprise first and second portions in the respective trenches, and the gate connector has a different conductivity than the first portions (i.e. see at least Figures 4-7, the gate polysilicon 8 is formed earlier than the polysilicon 27 in Figure 5; for the gate polysilicon 8, in-situ doping at deposition is straight-forward and enables high doping levels, since doping by implantation would be more difficult in the trenches; in contrast, polysilicon layer 27 has to be initially formed without doping or at a low doping concentration to enable formation of a diode; therefore, a commonplace recess of the gate electrode in conjunction with a separate doping of the upper part forming the connection portions in each trench will normally result in an upper gate polysilicon portion that is less doped).
In re claim 26, Fujii discloses wherein the first portions of the gates have a greater conductivity than the second portions of the gates (i.e. see at least Figures 4-7, the gate polysilicon 8 is formed earlier than the polysilicon 27 in Figure 5; for the gate polysilicon 8, in-situ doping at deposition is straight-forward and enables high doping levels, since doping by implantation would be more difficult in the trenches; in contrast, polysilicon layer 27 has to be initially formed without doping or at a low doping concentration to enable formation of a diode; therefore, a commonplace recess of the gate electrode in conjunction with a separate doping of the upper part forming the connection portions in each trench will normally result in an upper gate polysilicon portion that is less doped).
In re claim 29, Fujii discloses wherein the gate connector has a same conductivity as the second portions of the gates (i.e. see at least Figures 4-7, the gate polysilicon 8 is formed earlier than the polysilicon 27 in Figure 5; for the gate polysilicon 8, in-situ doping at deposition is straight-forward and enables high doping levels, since doping by implantation would be more difficult in the trenches; in contrast, polysilicon layer 27 has to be initially formed without doping or at a low doping concentration to enable formation of a diode; therefore, a commonplace recess of the gate electrode in conjunction with a separate doping of the upper part forming the connection portions in each trench will normally result in an upper gate polysilicon portion that is less doped).
In re claim 30, Fujii discloses wherein the at least one integrated polysilicon device is electrically isolated from the gate connector devoid of an inter-polysilicon dielectric layer therebetween (i.e. the inter-polysilicon dielectric layer is understood to be a layer vertically separating polysilicon layers as shown in prior art Figure 8 of the instant application, there is no such layer in Figure 2 of Fujii).
Allowable Subject Matter
Claims 20, 27, and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
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/ANTHONY HO/Primary Examiner, Art Unit 2817
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