DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/30/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Matsuoka (US Pub. 2004/0095805) in view of Ishii (US Pub. 2019/0088289).
Regarding claim 1, Fig. 2 of Matsuoka discloses a memory device comprising:
a memory array comprising a plurality of memory cells [M11 to M1j], a first terminal of each of the plurality of memory cells is connected to a bit line [Bit], a second terminal of each of the plurality of memory cells is connected to a source line [S1], and a third terminal of each of the plurality of memory cells is connected to a word line [WL1], wherein the word line is associated with a word line address [paragraph 0035. Also, since each word line is outputted a word line decoder, it is inherently associated with a word line address], and
a resistance trimming circuit [2] connected to either the source line [S1], the bit line or a common source line and configured to receive a trimming code [Address signal] to change an equivalent resistance of the source line or the bit line based on the trimming code [paragraph 0074], wherein the trimming code is tied to the word line address [paragraphs 0035 and 0076].
Matsuoka discloses all claimed invention, but does not specifically disclose a third terminals of the plurality of memory cells are connected to the plurality of word lines in one-by-one manner, wherein each of the plurality of word lines is associated with a word line address. However, Fig. 16 of Ishii discloses a memory device with trimming circuit [Variable resistance circuit] that is controlled by word line address [from Row decoder] having plurality of memory cells [MC], wherein each memory cell having disclose a third terminals of the plurality of memory cells [MC column that is connected to LBL0] are connected to the plurality of word lines [WL0 to WL3] in one-by-one manner [each memory cell in LBL0 column is connected to each word line], wherein each of the plurality of word lines is associated with a word line address [row addresses that are used by Row decoder to select one of the wordlines (WL0 to WL3)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Ishii’s memory device having multiple wordlines to the teachings of Matsuoka’s memory having plurality of memory cells such that Matsuoka’s memory device having plurality of memory cells in the same column connects to different wordline according to Ishii’s teachings for a purpose of correcting variation of resistance value on the bit lines [paragraph 0087].
Regarding claims 2 and 12, Fig. 2 of Matsuoka discloses wherein the word line address has X bits [2 bits, since 20= 1, one word line WL1] , the trimming code is most significant Y bits [2] of the X bits [2], and Y ≤ X [Y ≤ X, which is 2 ≤ 2] wherein X and Y are integers greater than 0 [they both equal 2].
Regarding claims 3 and 13, Fig. 2 of Matsuoka discloses wherein the resistance trimming circuit comprising a plurality of trimming switches [two switches, ST1 and ST2] and a plurality of resistors [R1 and R2], each of the plurality of trimming switches is turned on or off according to the trimming code [Address signal] which corresponds to a value of the most significant Y bits [2 bits] of the X bits of the word line address to deactivate or activate a corresponding resistor of the plurality of resistors.
Regarding claims 4 and 14, Fig. 2 of Matsuoka discloses wherein a quantity of the plurality of trimming switches is equal to Y [2].
Regarding claims 5 and 15, Fig. 2 of Matsuoka discloses wherein a quantity of the plurality of resistors [two resistors (R1, R2)] is the same as the quantity of the plurality of trimming switches [two switches, ST1 and ST2].
Regarding claims 6 and 16, Fig. 2 of Matsuoka discloses wherein the plurality of resistors comprising: a first resistor [R1] connected to either the source line [S1] or the bit line, and a second resistor [R2] connected to the first resistor [R1] in series, and the plurality of trimming switches comprising: a first trimming switch [ST1] connected to the first resistor [R1] in parallel, and a second trimming switch [ST2] connected to the second resistor [R2] in parallel.
Regarding claim 7, Fig. 2 of Matsuoka discloses wherein in response to at least the first trimming switch [ST1] and the second trimming switch [St2] having been deactivated by the trimming code [Address signal], the equivalent resistance of the bit line or the source line [S1] increases by at least a first resistance of the first resistor in addition to a second resistance of the second resistor [paragraph 0079].
Regarding claims 8 and 18, Fig. 2 of Matsuoka discloses a word line address decoder [as discloses in paragraph 0006 and 0007. There can be plurality of word lines. Since there are plurality of word lines, a word line decoder is inherent to select a word line] which provides the trimming code [address signal] which decodes the word line address to obtain the most significant Y bits of the X bits of the word line address as the trimming code [paragraph 0035].
Regarding claims 9 and 19, Fig. 2 of Matsuoka discloses wherein one terminal of the resistance trimming circuit is connected to the source line [S1] and another terminal of the resistance trimming circuit is connected to a source line driver [2a].
Regarding claims 10 and 20, Fig. 2 of Matsuoka discloses wherein the resistance trimming circuit [2] is connected to the common source line [S1].
Regarding claim 11, Fig. 2 of Matsuoka discloses a method of controlling an equivalent resistance of a bit line [Bit] or a source line [S1] connected to a plurality of memory cells [M11 to M1j] of a memory device, wherein a first terminal of each of the plurality of memory cells is connected to the bit line [Bit], a second terminal of each of the plurality of memory cells is connected to the source line [S1], and a third terminal of each of the plurality of memory cells is connected to a word line [WL1], the method comprising:
receiving a trimming code [Address signal] which is tied to a word line address [paragraph 0035];
activating or deactivating each resistor of a plurality of resistors [R1 to R2] of a resistance trimming circuit [2] connected to either the source line [S1], the bit line or a common source line based on the trimming code [Address signal] to change the equivalent resistance of the source line [paragraph 0074] or the bit line; and
activating or deactivating the plurality of memory cells [M11 to M1j] of a word line according to the word line address [word line is inherently controlled to row (word line) address].
Matsuoka discloses all claimed invention, but does not specifically disclose a third terminals of the plurality of memory cells are connected to the plurality of word lines in one-by-one manner, wherein each of the plurality of word lines is associated with a word line address. However, Fig. 16 of Ishii discloses a memory device with trimming circuit [Variable resistance circuit] that is controlled by word line address [from Row decoder] having plurality of memory cells [MC], wherein each memory cell having disclose a third terminals of the plurality of memory cells [MC column that is connected to LBL0] are connected to the plurality of word lines [WL0 to WL3] in one-by-one manner [each memory cell in LBL0 column is connected to each word line], wherein each of the plurality of word lines is associated with a word line address [row addresses that are used by Row decoder to select one of the wordlines (WL0 to WL3)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Ishii’s memory device having multiple wordlines to the teachings of Matsuoka’s memory having plurality of memory cells such that Matsuoka’s memory device having plurality of memory cells in the same column connects to different wordline according to Ishii’s teachings for a purpose of correcting variation of resistance value on the bit lines [paragraph 0087].
Regarding claim 17, Fig. 2 of Matsuoka discloses increasing the equivalent resistance of the bit line or the source line [S1] by at least a first resistance [R1] of the first resistor in addition to a second resistance of the second resistor [R2] in response to at least the first trimming switch [Address signal] and the second trimming switch [ST2] having been deactivated by the trimming code.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANTHAN TRAN/Primary Examiner, Art Unit 2825