DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-8, 10, 11, 15-22, 39 in the reply filed on 05/14/26 is acknowledged. The traversal is on the ground(s) that that there is no serious burden in examining the listed inventions simultaneously. This is not found persuasive because classification is one avenue where a search may pose a burden.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10, 11, 15-22, 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mahmoud(USPGPUB DOCUMENT: 2020/0295202, hereinafter Mahmoud) in view of Akiyama (USPGPUB DOCUMENT: 2011/0227068, hereinafter Akiyama).
Re claim 1 Mahmoud discloses a semiconductor device, comprising:a substrate(substrate of M1/M2)[0019]; and a plurality of semiconductor layers(110/120/130) on the substrate(substrate of M1/M2)[0019], the plurality of semiconductor layers(110/120/130) in a stacked arrangement.
Mahmoud does not discloses the plurality of semiconductor layers(110/120/130) being bonded to one another
Akiyama discloses the plurality of semiconductor layers(3/5/1) being bonded to one another [0065]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Akiyama to the teachings of Mahmoud in order to minimize the crack or chip of the bonded wafer, detachment at the bonded surfaces etc. from being caused by a difference in coefficient of thermal expansion between the wide bandgap semiconductor substrate and the handle substrate. [0014, Akiyama].
Re claim 2 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein the plurality of semiconductor layers(110/120/130) comprises:a first semiconductor layer having a first doped region[0019]; a second semiconductor layer having a second doped region[0019]; and wherein the first semiconductor layer and the second semiconductor layer are in the stacked arrangement such that the first doped region[0019] is aligned with the second doped region[0019].
Re claim 3 Mahmoud and Akiyama disclose the semiconductor device of claim 2, wherein the first doped region[0019] and the second doped region[0019] each have a first conductivity type.
Re claim 4 Mahmoud and Akiyama disclose the semiconductor device of claim 2, wherein the first doped region[0019] has a first conductivity type and the second doped region[0019] has a second conductivity type.
Re claim 5 Mahmoud and Akiyama disclose the semiconductor device of claim 2, wherein the first doped region[0019] and the second doped region[0019] each comprise implanted dopants.
Re claim 6 Mahmoud and Akiyama disclose the semiconductor device of claim 2, wherein the first doped region[0019] has a first dopant concentration[0027] and the second doped region[0019] has a second dopant concentration[0027], the first dopant concentration[0027] being different than the second dopant concentration[0027].
Re claim 7 Mahmoud and Akiyama disclose the semiconductor device of claim 2, wherein the plurality of semiconductor layers(110/120/130) comprises a third semiconductor layer having a third doped region[0019], wherein the third semiconductor layer is in the stacked arrangement such that third doped region[0019] is aligned with the first doped region[0019] and the second doped region[0019].
Re claim 8 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein the plurality of semiconductor layers(110/120/130) comprises a first semiconductor layer having a first doped region[0019] proximate a first surface of the first semiconductor layer and a second doped region[0019] proximate a second surface of the first semiconductor layer, the second surface of the first semiconductor layer being opposite the first surface of the first semiconductor layer.
Re claim 10 Mahmoud and Akiyama disclose the semiconductor device of claim 8, wherein the plurality of semiconductor layers(110/120/130) comprises a second semiconductor layer having a third doped region[0019] proximate a first surface of the second semiconductor layer and a fourth doped region[0019] proximate a second surface of the second semiconductor layer, the second surface of the second semiconductor layer being opposite the first surface of the second semiconductor layer.
Re claim 11 Mahmoud and Akiyama disclose the semiconductor device of claim 10, wherein the first semiconductor layer and the second semiconductor layer are in the stacked arrangement such that the first doped region[0019], the second doped region[0019], the third doped region[0019], and the fourth doped region[0019] are aligned.
Re claim 15 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein each of the plurality of semiconductor layers(110/120/130) has a thickness[0083] in a range of about 0.05 microns to about 200 microns.
Re claim 16 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein the plurality of semiconductor layers(110/120/130) each comprise silicon carbide or a Group III-nitride.
Re claim 17 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein each of the plurality of semiconductor layers(110/120/130) is a separated portion of one or more wide bandgap epitaxial semiconductor structures.
Re claim 18 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein a first semiconductor layer of the plurality of semiconductor layers(110/120/130) is a different material relative to a second semiconductor layer of the plurality of semiconductor layers(110/120/130).
Re claim 19 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein the substrate(substrate of M1/M2)[0019] comprises silicon carbide.
Re claim 20 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein the substrate(substrate of M1/M2)[0019] comprises polycrystalline silicon carbide.
Re claim 21 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein the semiconductor device comprises a JFET[0036], MOSFET, Schottky diode, or an IGBT.
Re claim 22 Mahmoud and Akiyama disclose the semiconductor device of claim 1, wherein the semiconductor device comprises a bipolar-CMOS-DMOS device[0056].
Re claim 39 Mahmoud discloses a semiconductor device, comprising:a substrate(substrate of M1/M2)[0019]; a semiconductor structure comprising a plurality of semiconductor layers(110/120/130) on the substrate(substrate of M1/M2)[0019], the plurality of semiconductor layers(110/120/130) in a stacked arrangement; wherein at least one of the plurality of semiconductor layers(110/120/130) comprises a doped column, the doped column having a thickness[0083] of about 2 microns or greater; and a gate contact(14) on the doped column.
Mahmoud does not discloses the plurality of semiconductor layers(110/120/130) being bonded to one another
Akiyama discloses the plurality of semiconductor layers(3/5/1) being bonded to one another [0065]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Akiyama to the teachings of Mahmoud in order to minimize the crack or chip of the bonded wafer, detachment at the bonded surfaces etc. from being caused by a difference in coefficient of thermal expansion between the wide bandgap semiconductor substrate and the handle substrate. [0014, Akiyama].
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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