Prosecution Insights
Last updated: July 17, 2026
Application No. 18/430,868

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FABRICATING SAME

Non-Final OA §102§112
Filed
Feb 02, 2024
Examiner
GARCES, NELSON Y
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
471 granted / 587 resolved
+12.2% vs TC avg
Minimal +3% lift
Without
With
+2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
28 currently pending
Career history
631
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
76.6%
+36.6% vs TC avg
§102
15.9%
-24.1% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 587 resolved cases

Office Action

§102 §112
DETAILED ACTION This action is responsive to the application No. 18/430,868 filed on February 02, 2024. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election without traverse of the Group II invention in the reply filed on 05/28/2026 is acknowledged. The Applicants indicated that claims 1-7 and 18-20 read on the elected invention. Accordingly, pending in this Office action are claims 1-7, 18-20 and newly added claims 21-320. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “a second cavity length” twice (in line 24 and line 26). It is unclear whether the second recited “a second cavity length” was intended to relate back to “a second cavity length” (line 24) or to set forth an additional second cavity length. Claim 30 recites the limitation “the at least one resonator VIA”. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 23 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 2019/0304929). Regarding Claim 23, Yang (see, e.g., Fig. 12, and Annotated Fig. 12), teaches a method of fabricating a semiconductor device, comprising: forming a plurality of resonator cavity wall metal components 2451/2452 in a first dielectric component 209, each of the plurality of resonator cavity wall metal components 2451/2452 associated with a distinct resonator cavity formed to extend into the first dielectric component 209, and each of the resonator cavities formed to have a different cavity length L1/L2 extending into the first dielectric component 209 (see, e.g., par. 0034); forming a second dielectric component 213 on the first dielectric component 209 (see, e.g., par. 0034); forming a planer capping metal layer CL on the second dielectric component 213 (see, e.g., par. 0034); and forming at least one capping metal VIA 249 extending through the second dielectric component 213 to the plurality of resonator cavity wall metal components 2451/2452 (see, e.g., par. 0034). Regarding Claim 30, Yang teaches all aspects of claim 23. Yang (see, e.g., Fig. 12, and Annotated Fig. 12), teaches forming a glue layer 247 between the at least one resonator via and at least one layer of the first dielectric component 209 (see, e.g., par. 0034). PNG media_image1.png 334 504 media_image1.png Greyscale Allowable subject matter Claims 18-22 are allowed. Claims 24-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garces whose telephone number is (571) 272-8249. The examiner can normally be reached on Mon-Fri 9:00 AM-5:30 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy can be reached on (571) 272-1705. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nelson Garces/Primary Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Feb 02, 2024
Application Filed
Jul 09, 2026
Non-Final Rejection mailed — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684861
SUBSTRATE ISOLATED STRAINED GATE-ALL-AROUND FIELD EFFECT TRANSISTOR
2y 9m to grant Granted Jul 14, 2026
Patent 12685172
INTEGRATED CIRCUIT WITH DIELECTRIC LAYER HAVING SELECTIVELY IMPLANTED STRESS-SETTING DOPANTS
2y 9m to grant Granted Jul 14, 2026
Patent 12672549
LIGHT SENSOR FOR PACKAGE INTRUSION DETECTION
2y 11m to grant Granted Jun 30, 2026
Patent 12672448
DISPLAY PANEL AND DISPLAY APPARATUS
2y 9m to grant Granted Jun 30, 2026
Patent 12666728
MONOLITHIC FOCAL PLANE ARRAY CIRCUIT AND METHOD THEREOF
2y 8m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
83%
With Interview (+2.7%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 587 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month