DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of Species I shown In FIGS. 1 and 2, reading on Claims 1-9 and 12-16, without traverse is acknowledged. Examiner notes that Claim 12 depend off Claims 11, hence should be withdrawn by virtue of their dependence off a withdrawn claim. Claims 10-12 and 17 are withdrawn from consideration.
Information Disclosure Statement
The information disclosure statement filed 07/02/2025 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 and 13-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YANG (US 2021/0265475), (hereinafter, YANG).
RE Claims 1, TANG discloses in FIGS. 1-21 a semiconductor device and a method of making the same. TANG discloses in FIG. 21 a semiconductor structure, comprising:
a substrate 101, having an array region 103 and a periphery region 105;
a first buried gate structure 207/205/203, extended from a first surface of the substrate 101 along a first direction “Z-direction” into the substrate and disposed in the array region 103; and
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a second buried gate structure 307/305/303, extended from the first surface of the substrate 101 along the first direction “Z-direction” into the substrate 101 and disposed in the periphery region 105,
wherein a depth of the first buried gate structure 207/205/203 is less than a depth of the second buried gate structure 307/305/303 along the first direction “Z-direction”.
RE Claims 2, TANG discloses a semiconductor structure, further comprising:
a first isolation structure 107 and a second isolation structure 107, disposed in the array region 103 of the substrate 101; and
a third isolation structure 109 and a fourth isolation structure 109, disposed in the periphery region 105 of the substrate 101,
wherein the first buried gate structure 207/205/203 is disposed between the first isolation structure 107 and the second isolation structure 107, and the second buried gate structure 307/305/303 is disposed between the third isolation structure 109 and the fourth isolation structure 109.
RE Claims 3, TANG discloses a semiconductor structure, wherein the substrate 101 comprises an active area 401 “formed of at least first doped area 401”, wherein the active area is coplanar with the first surface “upper surface” of the substrate 101, wherein a depth of the active area 401 “formed of at least first doped area 401” is less than the depth of the first buried gate structure 207/205/203.
RE Claims 4, TANG discloses a semiconductor structure, wherein the active area comprises:
a first doped region 401 and a second doped 401 region, disposed in the array region 103; and
a third doped region 403 and a fourth doped region 403, disposed in the periphery region 105,
wherein the first buried gate structure 207/205/203 is disposed between the first doped region 401 and the second doped region 401, and the second buried gate structure 307/305/303 is disposed between the third doped region 403 and the fourth doped region 403.
RE Claims 5, TANG discloses a semiconductor structure, wherein the first buried gate structure 207/205/203 has a first protruding portion protruding from the active area 401 toward a second surface “bottom surface” of the substrate 101, and the second buried gate structure 307/305/303 has a second protruding portion protruding from the active area 403 toward the second surface “bottom surface” of the substrate 101, wherein the second surface is opposite to the first surface, referring to FIG. 21. Examiner considers that the extended depth, particularly the rounded bottom edge extensions of the first and second gate structures 207/205/203 - 307/305/303, respectively represent the first and second protrusions, hence meeting the claimed limitations.
RE Claims 6, TANG discloses a semiconductor structure, wherein the substrate further comprises a first channel region and a second channel region, examiner notes that the limitation is inherently met since the channel lies under the gate electrode, and in the case of a buried trench gate of TANG device structure the channel region will surround the entire buried gate electrode, hence the claimed limitation is met,
wherein the first protruding portion of the first buried gate structure 207/205/203 is surrounded by the first channel region, and the second protruding portion of the second buried gate structure 307/305/303 is surrounded by the second channel region, referring to FIG. 21.
RE Claims 7, TANG discloses a semiconductor structure, wherein a first side length of the first protruding portion D1 is less than a second side length of the second protruding portion D2, referring to FIG. 21.
RE Claims 13, TANG discloses a semiconductor structure, further comprising:
a first metal line “metal silicide”, disposed in the doped region 405 over the substrate 101 and in contact with the first doped region 401; and
a second metal line “metal silicide”, disposed in the doped region 407 over the substrate 101 and in contact with the third doped region 403 [0078 and 0079].
RE Claims 14, TANG discloses a semiconductor structure, wherein a width “W1” of the first buried gate structure 207/205/203 is less than a width “W2” of the second buried gate structure 307/305/303 along a second direction “horizontal direction” perpendicular to the first direction “Z-direction”, referring to FIGS. 1 and 21.
RE Claims 15, TANG discloses a semiconductor structure, wherein
the first buried gate structure 207/205/203 comprises a first gate dielectric layer 203 and a first gate electrode 207, and the second buried gate structure 307/305/303 comprises a second gate dielectric layer 303 and a second gate electrode 307,
wherein the first gate electrode 207 is separated from the substrate 101 by the first gate dielectric layer 203, and the second gate electrode 307 is separated from the substrate by the second gate dielectric layer 303, referring to FIG. 21.
RE Claims 16, TANG discloses a semiconductor structure, wherein the first buried gate structure 207/205/203 further comprises a first capping layer, and the second buried gate structure further comprises a second capping layer,
wherein the first capping layer 209 is disposed over the first gate electrode 207 and separated from the substrate 101 by the first gate dielectric layer 203, and the second capping layer is disposed over the second gate electrode 307 and separated from the substrate 101 by the second gate dielectric layer 303, referring to FIG. 21.
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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