DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on May 18th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Election/Restrictions
Applicant's election without traverse of Species E of Invention II directed to Figs. 1-14 (claims 1-10 and new claims 21-31) in the reply filed on May 18th, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-23, 28 and 31 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zou et al. (Pub. No.: US 2024/0420990 A1), hereinafter as Zou.
Regarding claim 21, Zou discloses a method of forming semiconductor device in Fig. 1-2A, comprising: forming semiconductor layers (channel layers 112) extending over a substrate (substrate 102) (see Fig. 2A and [0062]); forming a gate structure (gate structure 210) wrapping around the semiconductor layers (see Fig. 2A and [0067]); forming gate spacers (inner spacers 214) on opposite sidewalls of the gate structure (see [0070]); depositing epitaxial source/drain structures (source/drains regions 208) on opposite sides of the gate structure (see Fig. 2A and [0067-0068]); forming a conductive contact (metal contact 230) over a first one of the epitaxial source/drain structures (left source/drain region 208) (see [0073-0074]); and forming a lower dielectric plug (lower portion of dielectric layer 220) over a second one of epitaxial source/drain structures (right source/drain region 208), wherein from a cross-sectional view, the gate spacers are between the lower dielectric plug and the conductive contact (inner spacer 214 between portion of dielectric layer 220 and metal contact 230) (see Fig. 2A and [0073]).
Regarding claim 22, Zou discloses the method of claim 21, further comprising: forming a conductive via (BEOL level 240) on the conductive contact (see Fig. 2A and [0056]); and forming an upper dielectric plug (upper portion of dielectric layer 220) on the lower dielectric plug (see Fig. 2A).
Regarding claim 23, Zou discloses the method of claim 21, wherein the gate structure has a top surface lower than a top surface of the upper dielectric plug (top surface of gate structure 210 comparing top surface of dielectric layer 220) (see Fig. 2A).
Regarding claim 28, Zou discloses the method of claim 21, wherein the lower dielectric plug comprises silicon oxide (see [0073]).
Regarding claim 31, Zou discloses the method of claim 21, further comprising: forming an upper dielectric plug (upper portion of dielectric layer 220) on the lower dielectric plug (lower portion of dielectric layer 220), wherein the upper dielectric plug has a lateral dimension different from a lateral dimension of the lower dielectric plug (see Fig. 2A).
Allowable Subject Matter
Claims 24-27 and 29-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Further comprising: forming a contact etch stop layer over the epitaxial source/drain structures prior to forming the lower dielectric plug over the second one of epitaxial source/drain structures as recited in claim 24.
Wherein the lower dielectric plug has a bottom surface higher than a bottom surface of the conductive contact as recited in claim 25.
Wherein a bottom surface of the lower dielectric plug has a first portion lower than a top surface of the gate structure and a second portion higher than the top surface of the gate structure as recited in claim 26.
Wherein the lower dielectric plug has a width decreasing in a direction toward the second one of the epitaxial source/drain structures as recited in claim 27.
Further comprising: a silicide layer between the lower dielectric plug and the second one of the epitaxial source/drain structures as recited in claim 29. Claim 30 depend on claim 29, and therefore also include said claimed limitation.
Claims 11-18, and 20 are allowed over prior art of record.
The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following:
Etching the ILD layer to form openings exposing the epitaxial source/drain structures; and forming a dielectric material in a first one of the openings and a conductive material in a second one of the openings as recited in claim 11. Claims 12-15 depend on claim 11, and therefore also include said claimed limitation.
Forming a second ILD layer over the first ILD layer, the functional contact and the dummy contact; etching the second ILD layer and the dummy contact to form a second opening; and depositing a dielectric material into the second opening as recited in claim 16. Claims 17-18 and 20 depend on claim 11, and therefore also include said claimed limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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