DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/05/2026 was considered by the examiner.
Response to Arguments
Applicant's arguments filed 02/04/2026 have been fully considered but they are not persuasive. Applicant recites on page 9 of remarks ” …that DiStefano and Guo do not disclose, teach or suggest the first insulating dielectric layer and the second insulating dielectric layer defined in claim 1…”. Referring to FIGS. 1-2 of DiStefano applicant further argues on pages 12 of remarks “…Each body 32 incorporates a first layer 38 of a flowable dielectric material at its first surface 34 and a second layer 40 of flowable dielectric material at its second major surface 36, as shown in FIG. 2”.
The examiner disagrees with applicant, since the prior art apparatus teaches all the structural limitations rather than the method steps of forming the dielectric layer, claim 1 is an apparatus claim.
Applicant further argues on pages 13-14 of remarks “…first layer 38 and the second layer 40 of the interposer 12a cannot independently exist, but need to be provided on the interior element 42, for example, by coating as mentioned in lines 1-12 of column 12. Accordingly, the first layer 38 and the second layer 40 are not independent dielectric layers, and cannot individually provided with through holes … each conductive element 48 is disposed in a single hole extending entirely through the body 32, not disposed in two through holes communicating with each other…”.
The examiner disagrees since the independence of the layers does not prevent them from being layers therefore the holes shown in FIGS. 1-2 of DiStefano do belong to each layer. An apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function or method steps. The prior art apparatus teaches all the structural limitations rather than the method steps of forming the dielectric layer in the circuit board.
In response to applicant's argument on page 14 that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., The hole containing the elements 72, 73 shown in FIG. 7 comes from the tapered holes 50, 51 shown in FIG. 3. Such a hole cannot be formed on the aforementioned interposer in DiStefano. As mentioned above, in DiStefano, the through hole of the interposer 12a is a continuous through hole, which is formed after the first laver 38 and the second laver 40 are provided on the interior element 42. In such condition, the shape of the through hole of the interposer 12a is limited to the straight hole as shown in FIG. 2 of DiStefano. Specifically, according to lines 14-19 of column 12 of DiStefano, the through hole may be formed by punching, drilling, laser cutting, or chemical etching. These processes cannot form such a complicated hole as two combined tapered holes or the like.) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Claim 1 is directed to an apparatus must be distinguished from the prior art in terms of structure rather than function or method steps.
Referring to FIG. 2 of RYU and FIG. 2a of Kwon, applicant further argues on pages 19-20 of remarks “…RYU and Kwon neither disclose nor teach that the holes in first and second layers are in direct communication with each other, and where Di Stefano expressly discloses and teaches that the first layer 38, the interior element 42 and the second layer 40 are combined as an integrated layer having a single straight hole without distinguishable upper and lower hole ends at an interface thereof, even if the teachings of RYU and Kwon were applied to DiStefano, a person having ordinary skill in the art would not have been motivated, without impermissible hindsight, to arrive at each and every feature of claim 5 by combining DiStefano…”
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
In response to applicant's argument on page 20 that ” …The interposer in DiStefano is designed without any horizontal wiring. If such horizontal wiring as the circuit patterns in RYU and Kwon are added to the interposer in DiStefano, the flowability of the interposer in Di Stefano will be compromised, and thereby the design purpose thereof cannot be achieved. Accordingly, a person having ordinary skill in the art would not have been taught to apply the structures disclosed in RYU and Kwon to the interposer of DiStefano so as to achieve the interval relationship between adjacent through holes at an interface as defined in claim 5…”. In view of the above, Di Stefano, RYU, and Kwon do not disclose, teach or suggest each and every feature of claim 5, particularly the features related to the attached first and second insulating dielectric layers, the interval relationships between two adjacent first through holes, and the interval relationship between two adjacent second through holes that are directly and respectively communicated with the two adjacent first through holes, such that DiStefano, RYU, and Kwon cannot achieve the technical effect provided by these features. Therefore, claim 5 is nonobvious over DiStefano, RYU, and Kwon, and is thus allowable.”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Applicant recites on pages 21-22 of remarks ”… Di Stefano and Guo do not disclose, teach or suggest the step of providing the first insulating dielectric layer, and the step of providing the second insulating dielectric layer defined in claim 9… the interposer 12a disclosed in Di Stefano is an integrated structure. The first layer 38 and the second layer 40 are not independent dielectric layers, and cannot individually provided with through holes. Therefore, the first layer 38 and the second layer 40 cannot be considered as the first and second insulating dielectric layers of the present application ... the through hole of the interposer 12a in Di Stefano is formed after the first layer 38 and the second layer 40 are provided on the interior element 42, and thereby cannot be shaped like two combined tapered holes. Therefore, PHOSIT A would not have had a reasonable expectation of success in combining the hole disclosed in Guo to the interposer in Di Stefano. Furthermore, if the holes containing the elements 72, 73 in Guo are applied to the interposer in DiStefano, the design purpose of the interposer in DiStefano cannot be achieved…”.
The examiner disagrees with applicant, since the prior art apparatus teaches all the structural limitations rather than the method steps of forming the dielectric layer in the circuit board.
In response to applicant’s argument on pages 21-22 that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). The courts have held that a change in shape or configuration, is within the level of skill in the art as the particular shape claimed by Applicant is nothing more than one of numerous shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Dailey, 149 USPQ 47 (CCPA 1976) and MPEP 2144.04.
Claims 2-4 and 6-8 remain rejected under by virtue of their dependence from claim 1 and 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over DiStefano et al. US 5367764 A in view of Guo et al. US 10881008 B1(hereinafter referred to as Guo).
Regarding claim 1, DiStefano discloses a circuit board for a semiconductor testing the circuit board comprising: a first substrate (fig. 1-3, circuit panel 10a, col. 13, ln. 16-18) having a lower surface (fig. 1-3, surface 18a, col. 15, ln. 40-41) and at least one first electrically conductive pad (fig. 1-3, conductors 24, col. 2, ln. 34-37) located on the lower surface of the first substrate; a second substrate (fig. 1-3, circuit panel 10b, col. 13, ln. 16-18) having an upper surface (fig. 1-3, surface 16, col. 8, ln. 24-32), and at least one second electrically conductive pad (fig. 1-3, conductors 22, col. 8, ln. 24-45) located on the upper surface of the second substrate; a first insulating dielectric layer (fig. 1-3, first layer 38, col. 7, ln. 55-61) having an upper surface (fig. 2-3, first major surface 34, col. 9, ln. 51-55), a lower surface (fig. 2-3, sheetlike interior element 42, col. 9, ln. 42-46) and at least one first through hole (fig. 2-3, plurality of holes, col. 11, ln. 1-5) the upper surface (34) of the first insulating dielectric layer (38) being attached to the lower surface (18a) of the first substrate (10a) having an upper end and a lower end the upper end (fig. 2-3, elm. 46a, and 47a, col. 14, ln. 11-18) of the first through hole being directly connected with the first electrically conductive pad (24), the upper end and the lower end of the first through hole; a second insulating dielectric layer (fig. 2-3, second layer 40, col. 9, ln. 56-60) having an upper surface (fig. 1-3, first major surface 42, col. 10, ln. 42-46), a lower surface (fig. 2-3, first surface 36, col. 9, ln. 56-60) and at least one second through hole (fig. 2-3, plurality of holes, col. 11, ln. 1-5) the upper surface and the lower surface of the second insulating dielectric layer (40) being attached to the lower surface of the first insulating dielectric layer (38) and the upper surface of the second substrate (see fig. 1-3, circuit panel 10b, col. 13, ln. 16-18) respectively, the second through hole having an upper end and a lower end, the lower end of the second through hole (fig. 2-3, plurality of holes, col. 11, ln. 1-5) being directly connected with the second electrically conductive pad (fig. 1-3, conductors 22 and 24, col. 8, ln. 47-60), the upper end of the second through hole directly communicating with the lower end of the first through hole, the upper end and the lower end of the second through hole (fig. 2-3, plurality of holes, col. 11, ln. 1-5); and at least one electrically conductive filler (fig. 2-3, conductive element 48, col. 11, ln. 11-13) disposed in the first through hole and the second through hole and electrically connected with the first electrically conductive pad and the second electrically conductive pad (fig. 2-3, col. 14, ln. 6-35).
DiStefano does not disclose the upper end and the lower end of the first through hole having a first upper width and a first lower width respectively, the first lower width being larger than the first upper width; the upper end and the lower end of the second through hole having a second upper width and a second lower width respectively, the second upper width being larger than the second lower width;
Guo discloses disclose the upper end (fig. 7, elm. 731, col. 4, ln. 11-6) and the lower end (fig. 7, elm. 732, col. 4, ln. 11-16) of the first through hole (fig. 7, hole containing elm. 73, col. 4, ln. 11-16) having a first upper width and a first lower width respectively, the first lower width being larger than the first upper width (fig. 7, col. 4, ln. 11-16); the upper end (fig. 7, elm. 731, col. 4, ln. 11-16) and the lower end of the second through hole (fig. 7, hole containing elm. 72, col. 4, ln. 5-10) having a second upper width (fig. 7, elm. 722, col. 4, ln. 5-10) and a second lower width (fig. 7, elm. 721, col. 4, ln. 5-10) respectively, the second upper width being larger than the second lower width.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a method for manufacturing the multi-layered circuit board, as taught in Guo in modifying the apparatus of DiStefano. The motivation would be the conductive paste filled hole reduces the difficulty for manufacturing fine lines or conductive holes with high width-to-thickness ratio (see Guo: background).
Regarding claim 2, DiStefano and Guo discloses the circuit board as claimed in claim 1, DiStefano discloses wherein the first electrically conductive pad (fig. 1-3, conductors 24, col. 13, ln. 40-41) of the first substrate (fig. 1-3, circuit panel 10a, col. 13, ln. 16-18) has a bottom surface directly connected with the upper end of the first through hole (fig. 2-3, plurality of holes, col. 11, ln. 1-5), and an outer peripheral surface (fig. 2-3, conductive material 28 in certain vias on each circuit panel electrically connects one or more conductors 22 on the first or top surface with one or more conductors 24 on the second or bottom surface of the panel, col. 8, ln. 56-60) located on an outer periphery of the bottom surface; the first insulating dielectric layer (fig. 1-3, first layer 38, col. 7, ln. 55-61) is attached to the outer peripheral surface (fig. 2-3, conductive elements 28 extending through each of the may constitute exposed conductive material at two separate interconnect locations on two opposite sides of the circuit panel, col. 13. ln. 44-48) and a part of the bottom surface of the first electrically conductive pad (fig. 1-3, conductors 24, col. 13, ln. 40-41); the second electrically conductive pad (fig. 1-3, conductors 22, col. 8, ln. 24-45) of the second substrate (see fig. 1-3, circuit panel 10b, col. 13, ln. 16-18) has a top surface directly connected with the lower end of the second through hole (fig. 2-3, plurality of holes, col. 11, ln. 1-5), and an outer peripheral surface located on an outer periphery of the top surface; the second insulating dielectric layer (fig. 2-3, second layer 40, col. 9, ln. 56-60) is attached to the outer peripheral surface (fig. 2-3, conductive material 28 in certain vias on each circuit panel electrically connects one or more conductors 22 on the first or top surface with one or more conductors 24 on the second or bottom surface of the panel, col. 8, ln. 56-60) and a part of the top surface of the second electrically conductive pad (see fig. 3).
Regarding claim 9, DiStefano and Guo discloses a method of manufacturing the circuit board of claim 1, DiStefano discloses the method comprising the steps of: providing a first substrate (fig. 1-3, circuit panel 10a, col. 13, ln. 16-18) and a second substrate (fig. 1-3, circuit panel 10b, col. 13, ln. 16-18), the first substrate having a lower surface (fig. 1-3, surface 18a, col. 15, ln. 40-41) and at least one first electrically conductive pad (fig. 1-3, conductors 24, col. 2, ln. 34-37) located on the lower surface of the first substrate, the second substrate having an upper surface (fig. 1-3, surface 16, col. 8, ln. 24-32) and at least one second electrically conductive pad ((fig. 1-3, surface 22, col. 8, ln. 24-45) located on the upper surface of the second substrate; providing a first insulting dielectric layer (fig. 1-3, first layer 38, col. 7, ln. 55-61) having an upper surface (fig. 2-3, first major surface 34, col. 9, ln. 51-55) attached to the lower surface of the first substrate; wherein the first insulting dielectric layer is configured as having at least one first through hole (fig. 2-3, plurality of holes, col. 11, ln. 1-5) made by drilling (col. 12, ln. 12-18) in a way that an upper end of the first through hole is directly connected with the first electrically conductive pad, a lower end of the first through hole is located on a lower surface (fig. 2-3, sheetlike interior element 42, col. 9, ln. 42-46) of the first insulating dielectric layer; providing a second insulating dielectric layer (fig. 2-3, second layer 40, col. 9, ln. 56-60) having a lower surface (fig. 2-3, first surface 36, col. 9, ln. 56-60) attached to the upper surface (16) of the second substrate; wherein the second insulating dielectric layer is configured as having at least one second through hole (fig. 2-3, plurality of holes, col. 11, ln. 1-5) made by drilling in a way that a lower end of the second through hole is directly connected with the second electrically conductive pad, an upper end of the second through hole is located on an upper surface (fig. 2-3, second layer 40, col. 9, ln. 56-60) of the second insulating dielectric layer and providing an electrically conductive filler (fig. 2-3, conductive element 48, col. 11, ln. 11-13) disposed in the first through hole and the second through hole in a way that the lower surface of the first insulating dielectric layer is attached to the upper surface of the second insulating dielectric layer, the upper end of the second through hole directly communicates with the lower end of the first through hole (see fig. 2-3), and the electrically conductive filler is electrically connected with the first electrically conductive pad and the second electrically conductive pad (fig. 2-3, col. 14, ln. 6-35).
DiStefano does not disclose the upper end and the lower end of the first through hole have a first upper width and a first lower width respectively, and the first lower width is larger than the first upper width; the upper end and the lower end of the second through hole have a second upper width and a second lower width respectively, and the second upper width is larger than the second lower width;
Guo discloses the upper end (fig. 7, elm. 731, col. 4, ln. 11-6) and the lower end (fig. 7, elm. 732, col. 4, ln. 11-16) of the first through hole (fig. 7, hole containing elm. 73, col. 4, ln. 11-16) have a first upper width and a first lower width respectively, and the first lower width is larger than the first upper width (fig. 7, col. 4, ln. 11-16);
the upper end (fig. 7, elm. 722, col. 4, ln. 5-10) and the lower end (fig. 7, elm. 721, col. 4, ln. 5-10) of the second through hole have a second upper width and a second lower width respectively, and the second upper width is larger than the second lower width (fig. 7, col. 4, ln. 5-16);
The references are combined for the same reason already applied in the rejection of claim 1.
Claim(s) 3-4 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over DiStefano in view of Guo as applied to claim 1 above, and further in view of US RYU et al. 2022/0369458 A1 (hereinafter referred to as Ryu) in view of Kwon et al. KR 20220135944 A (hereinafter referred to as Kwon).
Regarding claim 3, DiStefano and Guo discloses the circuit board as claimed in claim 1, DiStefano discloses wherein the first substrate (fig. 1-3, circuit panel 10a, col. 13, ln. 16-18) comprises a plurality of said first electrically conductive pads (fig. 1-3, conductors 24, col. 13, ln. 40-41); the first insulating dielectric layer (fig. 1-3, first layer 38, col. 7, ln. 55-61) has a plurality of said first through holes (fig. 2-3, plurality of holes 20, col. 11, ln. 1-5); the upper ends of the first through holes (fig. 2-3, plurality of holes, col. 11, ln. 1-5), are directly connected with the first electrically conductive pads (fig. 1-3, conductors 24, col. 13, ln. 40-41) respectively; the second substrate (see fig. 1-3, circuit panel 10b, col. 13, ln. 16-18) has a plurality of said second electrically conductive pad (fig. 1-3, surface 22, col. 8, ln. 24-45); the second insulating dielectric layer (fig. 2-3, second layer 40, col. 9, ln. 56-60) has a plurality of said second through holes (fig. 2-3, plurality of holes, col. 11, ln. 1-5); the upper ends (fig. 1-3, first major surface 42, col. 10, ln. 42-46) of the second through holes directly communicate with the lower ends of the first through holes respectively (see fig. 2-3)); the lower ends (fig. 2-3, second interconnect location 47, col. 11 , ln. 1-5) of the second through holes are directly connected with the second electrically conductive pads (fig. 1-3, conductors 22, col. 8, ln. 24-45).
DiStefano and Guo do not disclose a smallest distance between the upper ends of two adjacent said first through holes is defined as a first upper interval; the first upper interval is larger than the first upper width; a smallest distance between the lower ends of two adjacent said second through holes is defined as a second lower interval; the second lower interval is larger than the second lower width.
Ryu discloses a smallest distance between the upper ends of two adjacent said first through holes (fig. 3, elm. 133, par. [0089]-[0095]) is defined as a first upper interval (fig. 3, w1+w5-w4,par. [0089]-[0095]); the first upper interval is larger than the first upper width (see fig. 10, W4, par. [0089]-[0095]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provides a printed circuit board and a method of manufacturing the same wherein a via part disposed between the first and second pads in the insulating layer; and wherein a width of the first pad is less than or equal to a width of a lower surface of the via part and upper surface of the via part is greater than the width of the lower surface of the via part, as taught in Ryu in modifying the apparatus of DiStefano and Guo. The motivation would be able to increase the separation distance between a plurality of via portions adjacent to each other, so that the circuit density can be increased. (see Ryu: par. [0034).
Kwon discloses a smallest distance between the lower ends of two adjacent said second through holes(fig. 2a, 2b, first via 141 and a second via 142, par. [0124]) is defined as a second lower interval (fig. 2a, 2b, w3-w2 +w4, par. [0111], [0123], [0128]); the second lower interval is larger than the second lower width (fig. 2a, 2b, w3, par. [0123], [0128]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention provide to circuit board capable of minimizing a pitch between a plurality of adjacent pads, as taught in Kwon in modifying the apparatus of DiStefano, Guo and Ryu. The motivation would be volume of a package substrate can be reduced. (see Kwon: abs.).
Regarding claim 4, DiStefano, Guo, Ryu and Kwon discloses the circuit board as claimed in claim 3, Ryu discloses wherein a smallest distance between the lower ends of two adjacent said first through holes is defined as a first lower interval (fig. 3, w5, par. [0089]-[0095]); the first lower interval is smaller than the first upper interval (fig. 3, w1+w5-w4,par. [0089]-[0095]).
The references are combined for the same reason already applied in the rejection of claim 3.
DiStefano, Guo and Ryu do not disclose a smallest distance between the upper ends of two adjacent said second through holes is defined as a second upper interval; the second upper interval is smaller than the second lower interval .
Kwon discloses a smallest distance between the upper ends of two adjacent said second through holes (fig. 2a, 2b, first via 141 and a second via 142, par. [0124]) is defined as a second upper interval (fig. 2a, 2b, 2w7 +w6, par. [0098]); the second upper interval is smaller than the second lower interval (fig. 2a, 2b, w3-w2 +w4, par. [0111], [0123], [0128]).
The references are combined for the same reason already applied in the rejection of claim 3.
Regarding claim 10, DiStefano, Ryu and Kwon discloses the method of manufacturing the circuit board of claim 5, the method comprising the steps of: providing a first substrate (fig. 1-3, circuit panel 10a, col. 13, ln. 16-18) and a second substrate (fig. 1-3, circuit panel 10b, col. 13, ln. 16-18), the first substrate having a lower surface (fig. 1-3, surface 18a, col. 15, ln. 40-41) and a plurality of first electrically conductive pads (fig. 1-3, conductors 24, col. 2, ln. 34-37) located on the lower surface of the first substrate, the second substrate having an upper surface (fig. 1-3, surface 16, col. 8, ln. 24-32) and a plurality of second electrically conductive pads (fig. 1-3, conductors 24, col. 2, ln. 34-37) located on the upper surface of the second substrate; providing a first insulating dielectric layer (fig. 1-3, first layer 38, col. 7, ln. 55-61) having an upper surface (fig. 2-3, first major surface 34, col. 9, ln. 51-55) attached to the lower surface of the first substrate; wherein the first insulating dielectric layer is configured as having a plurality of first through holes (fig. 2-3, plurality of holes, col. 11, ln. 1-5) made by drilling (col. 12, ln. 12-18) and each having an upper end and a lower end in a way that the upper ends of the first through holes are directly connected with the first electrically conductive pads respectively, the lower ends of the first through holes are located on a lower surface of the first insulating dielectric layer; providing a second insulating dielectric layer (fig. 2-3, second layer 40, col. 9, ln. 56-60) having a lower surface (fig. 2-3, first surface 36, col. 9, ln. 56-60) attached to the upper surface of the second substrate; wherein the second insulating dielectric layer is configured as having a plurality of second through holes (fig. 2-3, plurality of holes, col. 11, ln. 1-5) made by drilling (col. 12, ln. 12-18) and each having an upper end and a lower end in a way that the lower ends of the second through holes are directly connected with the second electrically conductive pads (fig. 1-3, surface 22, col. 8, ln. 24-45) respectively; and providing a plurality of electrically conductive fillers disposed in the first through holes and the second through holes in a way that the lower surface of the first insulating dielectric layer is attached to the upper surface (fig. 2-3, second layer 40, col. 9, ln. 56-60) of the second insulating dielectric layer (fig. 2-3, second layer 40, col. 9, ln. 56-60), the upper ends of the second through holes directly communicate with the lower ends of the first through holes respectively (see fig. 2-3), and each of the electrically conductive fillers (fig. 2-3, conductive element 48, col. 11, ln. 11-13) is disposed in the first through hole and the second through hole, which are communicated with each other, and electrically connected with one of the first electrically conductive pads and one of the second electrically conductive pads (fig. 2-3, col. 14, ln. 6-35).
DiStefano does not disclose smallest distance between the upper ends of two adjacent said first through holes is defined as a first upper interval, a smallest distance between the lower ends of two adjacent said first through holes is defined as a first lower interval, and the first lower interval is smaller than the first upper interval; a smallest distance between the lower ends of two adjacent said second through holes is defined as a second lower interval, a smallest distance between the upper ends of two adjacent said second through holes is defined as a second upper interval, and the second upper interval is smaller than the second lower interval
Ryu discloses a smallest distance between the upper ends of two adjacent said first through holes (fig. 3, elm. 133, par. [0089]-[0095])is defined as a first upper interval (fig. 3, w1+w5-w4,par. [0089]-[0095]); the first upper interval is larger than the first upper width;
Kwon discloses a smallest distance between the lower ends of two adjacent said second through holes (fig. 2a, 2b, first via 141 and a second via 142, par. [0124]) is defined as a second lower interval (fig. 2a, 2b, w3-w2 +w4, par. [0111], [0123], [0128]); the second lower interval is larger than the second lower width (fig. 2a, 2b, w3, par. [0123], [0128]).
The references are combined for the same reason already applied in the rejection of claim 3.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over DiStefano as applied to claim 5 above, and further in view of Ryu in view of Kwon.
Regarding claim 5, DiStefano discloses a circuit board for a semiconductor testing, the circuit board comprising: a first substrate (fig. 1-3, circuit panel 10a, col. 13, ln. 16-18) having a lower surface (fig. 1-3, surface 18a, col. 15, ln. 40-41), and a plurality of first electrically conductive pads (fig. 1-3, conductors 24, col. 2, ln. 34-37) located on the lower surface of the first substrate; a second substrate (fig. 1-3, circuit panel 10b, col. 13, ln. 16-18) having an upper surface (fig. 1-3, surface 16, col. 8, ln. 25-28), and a plurality of second electrically conductive pads (fig. 1-3, surface 22, col. 8, ln. 24-45) located on the upper surface (fig. 1-3, surface 16, col. 8, ln. 25-28), of the second substrate; a first insulating dielectric layer (fig. 2-3, first layer 38, col. 9, ln. 55-60) having an upper surface (fig. 1-3, first major surface 34, col. 9, ln. 51-55), a lower surface and a plurality of first through holes (fig. 2-3, plurality of holes, col. 11, ln. 1-5) the upper surface of the first insulating dielectric layer (38) being attached to the lower surface of the first substrate (10a), each of the first through holes having an upper end (fig. 2-3, Interconnect location 46a, col. 13, ln. 24-30) and a lower end, the upper ends of the first through holes being directly connected with the first electrically conductive pads (24) respectively (fig. 1-3, col. 13, ln. 7-47); a second insulating dielectric layer (fig. 1-3, second layer 40, col. 9, ln. 56-60), having an upper surface (fig. 1-3, first major surface 42, col. 10, ln. 42-46) a lower surface (fig. 1-3, second major surface 36, col. 9, ln. 51-55), and a plurality of second through holes (fig. 2-3, plurality of holes, col. 11, ln. 1-5), the upper surface and the lower surface of the second insulating dielectric layer (40) being attached to the lower surface of the first insulating dielectric layer and the upper surface of the second substrate (see fig. 1-3, circuit panel 10b, col. 13, ln. 16-18) respectively, each of the second through holes having an upper end and a lower end, the lower ends of the second through holes being directly connected with the second electrically conductive pads respectively (fig. 2-3), the upper ends of the second through holes directly communicating with the lower ends of the first through holes respectively (fig. 1-3, col. 13, ln. 7-47), a smallest distance between the lower ends of two adjacent said second through holes being defined as a second lower interval, a smallest distance between the upper ends of two adjacent said second through holes being defined as a second upper interval, the second upper interval being smaller than the second lower interval; and a plurality of electrically conductive fillers (fig. 2-3, elm. 48, col. 11, ln. 9-25), each of the electrically conductive fillers being disposed in the first through hole and the second through hole, which are communicated with each other (fig. 2-3, col. 14, 6-35), and electrically connected with one of the first electrically conductive pads and one of the second electrically conductive pads (fig. 3, col. 11, ln. 9-25).
DiStefano do not disclose a smallest distance between the upper ends of two adjacent said first through holes being defined as a first upper interval, a smallest distance between the lower ends of two adjacent said first through holes being defined as a first lower interval, the first lower interval being smaller than the first upper interval.
Ryu discloses a smallest distance between the upper ends of two adjacent said first through holes (fig. 3, elm. 133, par. [0089]-[0095]) is defined as a first upper interval (fig. 3, w1+w5-w4,par. [0089]-[0095]); the first upper interval is larger than the first upper width (see fig. 10, W4, par. [0089]-[0095]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provides a printed circuit board and a method of manufacturing the same wherein a via part disposed between the first and second pads in the insulating layer; and wherein a width of the first pad is less than or equal to a width of a lower surface of the via part and upper surface of the via part is greater than the width of the lower surface of the via part, as taught in Ryu in modifying the apparatus of DiStefano. The motivation would be able to increase the separation distance between a plurality of via portions adjacent to each other, so that the circuit density can be increased. (see Ryu: par. [0034).
Kwon discloses a smallest distance between the lower ends of two adjacent said second through holes (fig. 2a, 2b, first via 141 and a second via 142, par. [0124]) is defined as a second lower interval (fig. 2a, 2b, w3-w2 +w4, par. [0111], [0123], [0128]); the second lower interval is larger than the second lower width (fig. 2a, 2b, w3, par. [0123], [0128])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention provide to circuit board capable of minimizing a pitch between a plurality of adjacent pads, as taught in Kwon in modifying the apparatus of DiStefano and Ryu. The motivation would be volume of a package substrate can be reduced. (see Kwon: abs.).
Regarding claim 6, DiStefano, Ryu and Kwon discloses the circuit board as claimed in claim 5, Ryu discloses wherein the upper end and the lower end of each of the first through holes (fig. 3, elm. 133, par. [0089]-[0095]) have a first upper width (fig. 10, W4, par. [0089]-[0095]) and a first lower width (fig. 3, W4, par. [0092]) respectively; the first upper interval (fig. 3, w1+w5-w4,par. [0089]-[0095]) is larger than the first upper width (see fig. 3).
The references are combined for the same reason already applied in the rejection of claim 5.
Kwon discloses the upper end and the lower end of each of the second through holes (fig. 2a, 2b, first via 141 and a second via 142, par. [0124]) have a second upper width (fig. 2a, 2b, w1, par. [0123], [0126]) and a second lower width (fig. 2a, 2b, w3, par. [0123], [0128]) respectively; the second lower interval (fig. 2a, 2b, w3-w2 +w4, par. [0111], [0123], [0128]) is larger than the second lower width (see fig. 2a).
The references are combined for the same reason already applied in the rejection of claim 5.
Regarding claim 7, DiStefano, Ryu and Kwon discloses the circuit board as claimed in claim 5, Ryu discloses wherein the upper end and the lower end of each of the first through holes (fig. 3, elm. 133, par. [0089]-[0095]) have a first upper width (fig. 10, W4, par. [0089]-[0095]) and a first lower width (fig. 3, W4, par. [0092]) respectively; the first lower width is larger than the first upper width (see fig. 3).
The references are combined for the same reason already applied in the rejection of claim 5.
Kwon discloses the upper end and the lower end of each of the second through holes (fig. 2a, 2b, first via 141 and a second via 142, par. [0124]) have a second upper width (fig. 2a, 2b, w1, par. [0123], [0126]) and a second lower width (fig. 2a, 2b, w3, par. [0123], [0128]) respectively; the second upper width is larger than the second lower width (see fig. 2a).
The references are combined for the same reason already applied in the rejection of claim 5.
Regarding claim 8, DiStefano, Ryu and Kwon discloses the circuit board as claimed in claim 5, DiStefano discloses wherein each of the first electrically conductive pads (fig. 1-3, conductors 24, col. 13, ln. 40-41) of the first substrate (fig. 1-3, circuit panel 10a, col. 13, ln. 16-18) has a bottom surface (fig. 1-3, lower major surface 18a, col. 13, ln. 40-41) directly connected with the upper end of one of the first through holes (fig. 2-3, plurality of holes, col. 11, ln. 1-5), and an outer peripheral surface (fig. 2-3, conductive material 28 in certain vias on each circuit panel electrically connects one or more conductors 22 on the first or top surface with one or more conductors 24 on the second or bottom surface of the panel, col. 8, ln. 56-60) located on an outer periphery of the bottom surface; the first insulating dielectric layer (fig. 1-3, first layer 38, col. 7, ln. 55-61) is attached to the outer peripheral surface and a part of the bottom surface of each of the first electrically conductive pads (fig. 1-3, conductors 24, col. 13, ln. 40-41); each of the second electrically conductive pads (fig. 1-3, conductors 22, col. 8, ln. 24-45) of the second substrate (see fig. 1-3, circuit panel 10b, col. 13, ln. 16-18) has a top surface directly connected with the lower end of one of the second through holes (fig. 2-3, plurality of holes, col. 11, ln. 1-5), and an outer peripheral surface located on an outer periphery of the top surface (fig. 2-3, conductive material 28 in certain vias on each circuit panel electrically connects one or more conductors 22 on the first or top surface with one or more conductors 24 on the second or bottom surface of the panel, col. 8, ln. 56-60); the second insulating dielectric layer (fig. 2-3, second layer 40, col. 9, ln. 56-60) is attached to the outer peripheral surface and a part of the top surface of each of the second electrically conductive pads (see fig. 3).
DiStefano do not disclose the upper end and the lower end of the first through hole have a first upper width and a first lower width respectively, and the first lower width is larger than the first upper width, the upper end and the lower end of the second through hole have a second upper width and a second lower width respectively, and the second upper width is larger than the second lower
Ryu discloses the upper end and the lower end of the first through hole (fig. 3, elm. 133, par. [0089]-[0095]) have a first upper width (fig. 10, W4, par. [0089]-[0095]) and a first lower width (fig. 3, W4, par. [0092]) respectively, and the first lower width is larger than the first upper width (see fig. 3).
The references are combined for the same reason already applied in the rejection of claim 5.
Kwon discloses the upper end and the lower end of the second through hole (fig. 2a, 2b, first via 141 and a second via 142, par. [0124]) have a second upper width (fig. 2a, 2b, w1, par. [0123], [0126]) and a second lower width (fig. 2a, 2b, w3, par. [0123], [0128]) respectively, and the second upper width is larger than the second lower (see fig. 2a).
The references are combined for the same reason already applied in the rejection of claim 5.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 6/11/2026
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