Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant's election, without traverse, of claims 1-11 in the “Response to Restriction Requirement” filed on 08/11/2026 is acknowledged and entered by the Examiner.
This office action consider claims 1-20 pending for prosecution, wherein claims 12-20 are withdrawn from further consideration, and claims 1-11 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
1. Claims 1-11 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to
particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding Claim 1, the instant claim recites limitations, wherein the metes and bounds of the claimed method are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “a semiconductor substrate having a first surface and a second surface opposite to the first substrate, wherein the semiconductor substrate has at least one opening extending from the first surface to the second surface” (Claim 1, Lines 2-4; emphasis added). The claim is indefinite because of the following:
i) The claim is indefinite because “a semiconductor substrate having a first surface and a second surface opposite to the first substrate, wherein the semiconductor substrate has at least one opening extending from the first surface to the second surface” (Claim 1) lacks proper antecedent basis and is ambiguous and unclear. Firstly, there is no recitation of “a first substrate”. Secondly, it is not clear whether “the first substrate” is in reference to “a semiconductor substrate” or to another “first substrate”. Therefore, the limitation of “a semiconductor substrate having a first surface and a second surface opposite to the first substrate, wherein the semiconductor substrate has at least one opening extending from the first surface to the second surface” (Claim 1) is indefinite and unclear.
The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention.
As there is a great deal of confusion and uncertainty as to the proper interpretation of the limitations of the claim, it would not be proper for the examiner to reject such a claim on the basis of prior art. See MPEP § 706 and MPEP § 2173.II (second) wherein In re Steele, 305 F.2d 859, 134 USPQ 292 (CCPA 1962), a rejection under 35 U.S.C. 103 should not be based on considerable speculation about the meaning of terms employed in a claim or assumptions that must be made as to the scope of the claims.
Regarding Claims 2-11, those are rejected under 112(b) because of their dependency status from claim 1.
Regarding Claim 4, the instant claim recites limitations in view of the parent device claim 1, wherein the metes and bounds of the claimed method are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “wherein the second insulating layer partially fills the opening in the semiconductor substrate to form a hole between the through-substrate via and the second insulating layer in the opening” (Claim 4, Lines 1-3; emphasis added). The claim is indefinite because of the following:
i) The claim is indefinite because “wherein the second insulating layer partially fills the opening in the semiconductor substrate to form a hole between the through-substrate via and the second insulating layer in the opening” (Claim 4) lacks proper antecedent basis and is ambiguous and unclear. There is no recitation of “a first substrate”. Secondly, it is not clear whether “the first substrate” is in reference to “a through-substrate via” in claim 4 or claim 1. Therefore, the limitation of “wherein the second insulating layer partially fills the opening in the semiconductor substrate to form a hole between the through-substrate via and the second insulating layer in the opening” (Claim 4” (Claim 1) is indefinite and unclear.
The specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention, whereby the claims are rendered indefinite. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate clarification and/or correction are/is required within metes and bounds of the claimed invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1-5 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. (US 20180350747 A1; hereinafter Hwang).
Regarding claim 1, Hwang teaches a circuit substrate in a chip package (see the entire document, specifically Fig. 5; [0163+], and as cited below), comprising:
a semiconductor substrate ({300A: 100A, 200A}; Fig. 9; [0063]) having a first surface (top surface of {200A}; Fig. 9; [0063]) and a second surface (bottom surface of {200A}; Fig. 9; [0063]) opposite to the first substrate (see section 1, above; 112(b) rejection), wherein the semiconductor substrate ({300A: 100A, 200A}; Fig. 9; [0063]) has at least one opening (opening where 280 is present; Fig. 9; [0093]) extending from the first surface (top surface of {200A}; Fig. 9; [0063]) to the second surface (bottom surface of {200A}; Fig. 9; [0063]);
a first insulating layer (241; Fig. 9; [0103-0104]) and a second insulating layer (250; Fig. 9; [0107-0108]) covering the first surface (top surface of {200A}; Fig. 9; [0063]) and the second surface (bottom surface of {200A}; Fig. 9; [0063]) of the semiconductor substrate ({300A: 100A, 200A}; Fig. 9; [0063]), respectively;
a first pad (212a; Fig. 9; [0094]) and a second pad (232; Fig. 9; [0101-0102]) disposed in the first insulating layer (241; Fig. 9; [0103-0104]) and the second insulating layer (250; Fig. 9; [0107-0108]), respectively, and laterally separated from the opening; and
a first under-bump metallization layer (243; Fig. 9; [0103, 0105]) and a second under-bump metallization layer (260; Fig. 9; [0093, 0108]) disposed on the first pad (212a; Fig. 9; [0094]) and the second pad (232; Fig. 9; [0101-0102]), respectively;
wherein the first under-bump metallization layer (243; Fig. 9; [0103, 0105]) is surrounded by the first insulating layer (241; Fig. 9; [0103-0104]) and has a surface (the top portion of 243; Fig. 9; [0103, 0105]) protruding from the first insulating layer (241; Fig. 9; [0103-0104]);
wherein the second under-bump metallization layer (260; Fig. 9; [0093, 0108]) extends from the second pad (232; Fig. 9; [0101-0102]) onto the second insulating layer (250; Fig. 9; [0107-0108]) and is partially recessed into the second insulating layer (250; Fig. 9; [0107-0108]) to form a concave surface (260; Fig. 9; [0093, 0108]); and
wherein a width of the second under-bump metallization layer (260; Fig. 9; [0093, 0108]) is greater than (see Fig. 9, where the width of 260 is wider than a width of 243 when viewed in the left-right direction) a width of the first under-bump metallization layer (243; Fig. 9; [0103, 0105]).
Regarding claim 2, Hwang teaches all of the features of claim 1.
Hwang further comprising: a third pad (top portion of 280; Fig. 9; [0093, 0112]) disposed in the first insulating layer (241; Fig. 9; [0103-0104]) and substantially vertical to the opening in the semiconductor substrate; and a through-substrate via (middle portion of 280; Fig. 9; [0093, 0112]) disposed in the opening in the semiconductor substrate and electrically connected to the third pad (top portion of 280; Fig. 9; [0093, 0112]).
Regarding claim 3, Hwang teaches all of the features of claim 2.
Hwang further teaches wherein the through-substrate via (middle portion of 280; Fig. 9; [0093, 0112]) extends from the opening in the semiconductor substrate to between the second pad (232; Fig. 9; [0101-0102, 0112]) and the semiconductor substrate, and is electrically connected to the second pad (232; Fig. 9; [0101-0102, 0112]).
Regarding claim 4, Hwang teaches all of the features of claim 1.
Hwang further teaches wherein the second insulating layer (250; Fig. 9; [0107-0108]) partially fills the opening in the semiconductor substrate to form a hole between the through-substrate via (see section 1, above; 112(b) rejection) and the second insulating layer (250; Fig. 9; [0107-0108]) in the opening.
Regarding claim 5, Hwang teaches all of the features of claim 1.
Hwang further teaches wherein a material of the first insulating layer (241; Fig. 9; [0103-0104]) is different from a material of the second insulating layer (250; Fig. 9; [0107-0108]).
Regarding claim 8, Hwang teaches all of the features of claim 1.
Hwang further teaches wherein the chip package comprises: a semiconductor chip (120; Fig. 9; [0063]) disposed above the first surface (top surface of {200A}; Fig. 9; [0063]) of the semiconductor substrate; and a first conductive structure (160; Fig. 9; [0068]) electrically connected between the semiconductor chip (120; Fig. 9; [0063]) and the first under-bump metallization layer (243; Fig. 9; [0103, 0105]).
Regarding claim 9, Hwang teaches all of the features of claim 8.
Hwang further teaches wherein the chip package further comprises a second conductive structure (270; Fig. 9; [0093]) electrically connected to the second under-bump metallization layer (260; Fig. 9; [0093, 0108]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
3. Claim 6 is rejected under 35 U.S.C.103 as being unpatentable over Hwang et al. (US 20180350747 A1; hereinafter Hwang), in view of Yu et al. (US 20220223572 A1; hereinafter Yu).
Regarding claim 6, Hwang teaches all of the features of claim 5.
Hwang further teaches wherein the first insulating layer (241; Fig. 9; [0103-0104]; an insulating material) comprises (see below for “silicon oxide”), and the second insulating layer (250; Fig. 9; [0107-0108]) comprises an organic insulating material (see [0107-0108]).
As noted above, Hwang does not expressly disclose “wherein the first insulating layer comprises silicon oxide”.
However, in the analogous art, Yu teaches a package ([Abstract]), wherein (Fig. 1+; [0002+]) a dielectric layer (58; Fig. 6; [0025]) may be formed of inorganic and/or organic materials such as silicon oxide, silicon nitride, polyimide, polybenzoxazole (PB 0), or the like, where electrical connectors (60; [0026]) protrude above the dielectric layer (58; Fig. 6; [0025]) .
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to substitute Hwang’s silicon oxide material of the dielectric layer with Yu’s insulating material of the insulating layer, because they have equivalent properties, as recognized by Yu dielectric layer (58; Fig. 6; [0025]) may be formed of inorganic and/or organic materials such as silicon oxide, silicon nitride, polyimide, polybenzoxazole, or the like ([0025]), whereas modified Hwang teaches a insulating layer comprising an insulating material ([0104]). It has been held that the substitution of one prior teaching by another art supports an obviousness rejection, as in the instant case, the equivalency is being recognized in the prior art, and the substitution is then within the level of ordinary skill in the art. [MPEP 2144.06.II],
and thereby, modified Hwang’s (by Yu) device will have wherein the first insulating layer (Hwang 241; Fig. 9; [0103-0104]; an insulating material in view of insulating material of Yu 58; Fig. 6; [0025]; silicon oxide) comprises silicon oxide (in view of insulating material of Yu 58; Fig. 6; [0025]; silicon oxide), and the second insulating layer (Hwang 250; Fig. 9; [0107-0108]) comprises an organic insulating material (Hwang see [0107-0108]).
4. Claim 7 is rejected under 35 U.S.C.103 as being unpatentable over Hwang et al. (US 20180350747 A1; hereinafter Hwang), in view of Chang et al. (US 20240128218 A1; hereinafter Chang).
Regarding claim 7, Hwang teaches all of the features of claim 1.
Hwang further teaches wherein the first under-bump metallization layer (243; Fig. 9; [0103, 0105]) and the second under-bump metallization layer (260; Fig. 9; [0093, 0108]) each comprise: (see below for “a nickel layer; a palladium layer stacked on the nickel layer; and a gold layer stacked on the palladium layer”.
As noted above, Hwang does not expressly disclose “wherein the first insulating layer comprises wherein the first under-bump metallization layer and the second under-bump metallization layer each comprise: a nickel layer; a palladium layer stacked on the nickel layer; and a gold layer stacked on the palladium layer”.
However, in the analogous art, Chang teaches a semiconductor package ([Abstract]), wherein (Fig. 1+; [0002+]) a conductive bump comprising of a metal finish layer, where the metal finish layer may be formed of electroless nickel electroless palladium immersion gold (ENEPIG), which includes a nickel layer, a palladium layer on the nickel layer, and a gold layer on the palladium layer ([0019]), where the metal finish layer may include different materials and layers, and may be used to prevent the oxidation and the diffusion of the metal pillar to/from the solder cap .
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chang’s the composition of the metal finish layer into Hwang’s device, and thereby, modified Hwang’s (by Chang) device will have teaches wherein the first under-bump metallization layer (Hwang 243; Fig. 9; [0103, 0105] in view of Chang [0019]) and the second under-bump metallization layer (Hwang 260; Fig. 9; [0093, 0108] in view of Chang [0019]) each comprise: a nickel layer; a palladium layer stacked on the nickel layer; and a gold layer stacked on the palladium layer (in view of Chang [0019]; a nickel layer, a palladium layer on the nickel layer, and a gold layer on the palladium layer).
The ordinary artisan would have been motivated to modify Hwang in the manner set forth above, at least, because this inclusion provides a metal finish layer may be formed of electroless nickel electroless palladium immersion gold (ENEPIG), which includes a nickel layer, a palladium layer on the nickel layer, and a gold layer on the palladium layer, where the metal finish layer may include different materials and layers, and may be used to prevent the oxidation and the diffusion of the metal pillar to/from the solder cap (Chang [0019]).
5. Claims 10-11 are rejected under 35 U.S.C.103 as being unpatentable over Hwang et al. (US 20180350747 A1; hereinafter Hwang), in view of the following statement.
Regarding claim 10, Hwang teaches all of the features of claim 1.
Hwang further teaches wherein a ratio of a width of the opening (opening where 280 is present; Fig. 9; [0093]) in the semiconductor substrate to a thickness of the semiconductor substrate (see below for “is in a range from 1:1 to 1:3”).
As noted above, Hwang does not expressly disclose “wherein a ratio of a width of the opening in the semiconductor substrate to a thickness of the semiconductor substrate is in a range from 1:1 to 1:3”.
However, it has been held that “wherein a ratio of a width of the opening in the semiconductor substrate to a thickness of the semiconductor substrate is in a range from 1:1 to 1:3” will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such wherein a ratio of a width of the opening in the semiconductor substrate to a thickness of the semiconductor substrate is in a range from 1:1 to 1:3 is critical, “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation”. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). In this case, there is nothing in the present application to indicate that the claimed wherein a ratio of a width of the opening in the semiconductor substrate to a thickness of the semiconductor substrate is in a range from 1:1 to 1:3 is critical and will achieve unexpected results over the range outside of the claimed range. Therefore, it would have been obvious to have wherein a ratio of a width of the opening in the semiconductor substrate to a thickness of the semiconductor substrate is in a range from 1:1 to 1:3 as claimed in device because having the wherein a ratio of a width of the opening in the semiconductor substrate to a thickness of the semiconductor substrate is in a range from 1:1 to 1:3 can be optimized during routine experimentation depending upon a particular application.
The applicants have not established the criticality (see next paragraph below) of said first predetermined amount.
The specification contains no disclosure of either the critical nature of the claimed distance or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 11, Hwang teaches all of the features of claim 1.
Hwang further teaches wherein the second under-bump metallization layer (260; Fig. 9; [0093, 0108]) that is partially recessed into the second insulating layer (250; Fig. 9; [0107-0108]) forms a recess corresponding to the second pad (232; Fig. 9; [0101-0102]), and wherein a ratio of a depth of the recess (see Fig. 9) to a width of the recess (see below for “is in a range from 1:8. to 1:30”).
As noted above, Hwang does not expressly disclose “wherein the second under-bump metallization layer that is partially recessed into the second insulating layer forms a recess corresponding to the second pad, and wherein a ratio of a depth of the recess to a width of the recess is in a range from 1:8. to 1:30”
However, it has been held that “wherein the second under-bump metallization layer that is partially recessed into the second insulating layer forms a recess corresponding to the second pad, and wherein a ratio of a depth of the recess to a width of the recess is in a range from 1:8. to 1:30” will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such wherein the second under-bump metallization layer that is partially recessed into the second insulating layer forms a recess corresponding to the second pad, and wherein a ratio of a depth of the recess to a width of the recess is in a range from 1:8. to 1:30 is critical, “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation”. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). In this case, there is nothing in the present application to indicate that the claimed wherein the second under-bump metallization layer that is partially recessed into the second insulating layer forms a recess corresponding to the second pad, and wherein a ratio of a depth of the recess to a width of the recess is in a range from 1:8. to 1:30 is critical and will achieve unexpected results over the range outside of the claimed range. Therefore, it would have been obvious to have wherein the second under-bump metallization layer that is partially recessed into the second insulating layer forms a recess corresponding to the second pad, and wherein a ratio of a depth of the recess to a width of the recess is in a range from 1:8. to 1:30 as claimed in device because having the wherein the second under-bump metallization layer that is partially recessed into the second insulating layer forms a recess corresponding to the second pad, and wherein a ratio of a depth of the recess to a width of the recess is in a range from 1:8. to 1:30 can be optimized during routine experimentation depending upon a particular application.
The applicants have not established the criticality (see next paragraph below) of said first predetermined amount.
The specification contains no disclosure of either the critical nature of the claimed distance or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/OMAR F MOJADDEDI/Examiner, Art Unit 2898
Prosecution Insights