DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Information disclosure statements (IDS) were submitted on 4/26/24, 8/28/24 and 12/11/24. Accordingly, the information disclosure statements are being considered by the Examiner and initialed copies of the forms are attached to this correspondence.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2, 3, 8, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Adkisson et al. (US Patent Application Publication No. 2008/0073742) (“Adkisson”).
Regarding Claim 2, Adkisson teaches an image sensor device, comprising: a sensor die (Figure 3, item “IMAGING CHIP”) from a reconstituted wafer, the sensor die comprising an image sensor (see Figure 3) embedded in a dielectric layer (¶0032); and a processor die (Figure 3, item “LOGIC CHIP”) directly bonded to the sensor die without the use of an intervening adhesive.
Regarding Claim 3, Adkisson further teaches the processor die is communicatively coupled to the sensor die via direct hybrid bonds formed therebetween (see Figure 3, note direct hybrid bonds through item 37).
Regarding Claim 8, Adkisson further teaches the image sensor is a back side illuminated image sensor (see Figure 3).
Regarding Claim 9, Adkisson further teaches a first surface of the sensor die comprises an active surface of the image sensor, and a second surface of the sensor die opposite the first surface of the sensor die is bonded to the processor die (see Figure 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Adkisson as applied to Claim 2 above, and further in view of Chen et al. (US Patent Application Publication No. 2015/0171050) (“Chen”).
Regarding Claim 4, Adkisson teaches Claim 2 as indicated above. Adkisson does not specifically teach the dielectric layer is a first dielectric layer; the processor die comprises a second dielectric layer; and the first dielectric layer is directly bonded to the second dielectric layer. However, Chen teaches a method of bonding two devices together using direct hybrid bonding where each side of the bond comprises a dielectric layer (Figure 9, item 110 and 210) and a metal on each side inside the dielectric layers (Figure 9, item 118 and 218). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the dual dielectric layer structure of Chen in the bonded device of Adkisson, as Chen teaches such a bonding process reduces surface stress and allows the bonds to be substantially free of voids while being performed at lower temperatures (¶0042).
Regarding Claim 5, Chen further teaches the first dielectric layer includes one or more first metallic pads; the second dielectric layer includes one or more second metallic pads; and the processor die is communicatively coupled to the image sensor via direct hybrid bonds formed between the one or more first metallic pads and the one or more second metallic pads (see Figures 9 and 11A/B/C).
Regarding Claim 6, Chen further teaches the first dielectric layer and the second dielectric layer each comprise an oxide material (¶0025).
Regarding Claim 7, Chen further teaches the one or more first metallic pads and the one or more second metallic pads each comprise a copper material (¶0032).
Claims 10-21 are rejected under 35 U.S.C. 103 as being unpatentable over Adkisson in view of Chen.
Regarding Claim 10, Adkisson teaches an image sensor device, comprising: a sensor die (Figure 3, item “IMAGING CHIP”) from a reconstituted wafer, the sensor die comprising an image sensor (see Figure 3) embedded in a first dielectric layer (¶0032), wherein the first dielectric layer includes one or more first metallic pads (see Figure 3); and a processor die (Figure 3, item “LOGIC CHIP”).
Adkisson does not specifically teach the processor comprising a second dielectric layer, wherein the second dielectric layer includes one or more second metallic pads; and wherein the first dielectric layer and the second dielectric layer are directly bonded to one another without the use of an intervening adhesive; and wherein the processor die is communicatively coupled to the image sensor via direct hybrid bonds formed between the one or more first metallic pads and the one or more second metallic pads. However, Chen teaches a method of bonding two devices together using direct hybrid bonding where each side of the bond comprises a dielectric layer (Figure 9, item 110 and 210) and metal pads on each side inside the dielectric layers (Figure 9, item 118 and 218). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the dual dielectric layer structure of Chen in the bonded device of Adkisson, as Chen teaches such a bonding process reduces surface stress and allows the bonds to be substantially free of voids while being performed at lower temperatures (¶0042).
Regarding Claim 11, Chen further teaches the first dielectric layer and the second dielectric layer each comprise an oxide material (¶0025).
Regarding Claim 12, Chen further teaches the one or more first metallic pads and the one or more second metallic pads each comprise a copper material (¶0032).
Regarding Claim 13, Adkisson further teaches the image sensor is a back side illuminated image sensor (see Figure 3).
Regarding Claim 14, Adkisson further teaches a first surface of the sensor die comprises an active surface of the image sensor, and a second surface of the sensor die opposite the first surface of the sensor die is bonded to the processor die (see Figure 3).
Regarding Claim 15, Adkisson teaches an image sensor device, comprising: a sensor die (Figure 3, item “IMAGING CHIP”) from a reconstituted wafer, the sensor die comprising an image sensor (see Figure 3) and a first dielectric layer (¶0032); and a processor die (Figure 3, item “LOGIC CHIP”).
Adkisson does not specifically teach the processor comprising a second dielectric layer, wherein the second dielectric layer includes one or more second metallic pads; and wherein the first dielectric layer and the second dielectric layer are directly bonded to one another without the use of an intervening adhesive; and wherein the processor die is communicatively coupled to the image sensor via direct hybrid bonds formed between the one or more first metallic pads and the one or more second metallic pads. However, Chen teaches a method of bonding two devices together using direct hybrid bonding where each side of the bond comprises a dielectric layer (Figure 9, item 110 and 210) and metal pads on each side inside the dielectric layers (Figure 9, item 118 and 218). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the dual dielectric layer structure of Chen in the bonded device of Adkisson, as Chen teaches such a bonding process reduces surface stress and allows the bonds to be substantially free of voids while being performed at lower temperatures (¶0042).
Regarding Claim 16, Adkisson further teaches the processor die is communicatively coupled to the sensor die via direct hybrid bonds formed therebetween (see Figure 3, note direct hybrid bonds through item 37).
Regarding Claim 17, Chen further teaches the first dielectric layer includes one or more first metallic pads; the second dielectric layer includes one or more second metallic pads; and the processor die is communicatively coupled to the image sensor via direct hybrid bonds formed between the one or more first metallic pads and the one or more second metallic pads (see Figures 9 and 11A/B/C).
Regarding Claim 18, Chen further teaches the first dielectric layer and the second dielectric layer each comprise an oxide material (¶0025).
Regarding Claim 19, Chen further teaches the one or more first metallic pads and the one or more second metallic pads each comprise a copper material (¶0032).
Regarding Claim 20, Adkisson further teaches the image sensor is a back side illuminated image sensor (see Figure 3).
Regarding Claim 21, Adkisson further teaches a first surface of the sensor die comprises an active surface of the image sensor, and a second surface of the sensor die opposite the first surface of the sensor die is bonded to the processor die (see Figure 3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang et al. (US Patent No. 8,193,632)
Chun et al. (US Patent No. 9,461,007)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARK W. TORNOW
Primary Examiner
Art Unit 2891
/MARK W TORNOW/Primary Examiner, Art Unit 2891
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