DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 7/12/2026 that has been entered, wherein claims 16-35 are pending and claims 1-15 are canceled.
Election/Restrictions
Applicant’s election without traverse of Invention II, claims 16-35 in the reply filed on 7/12/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/28/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 4/1/2024. These drawings are acceptable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-31 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation "the two or more semiconductor layers " in line 6. There is insufficient antecedent basis for this limitation in the claim. Is the “two or more semiconductor layers” the same or different than the “ two or more semiconductor channel layers” in line 3? For the purpose of examination, “two or more semiconductor layers” will be interpreted as“ two or more semiconductor channel layers”.
Claim 21 recites the limitation "the two or more semiconductor channel " in line 11. There is insufficient antecedent basis for this limitation in the claim. Is the “two or more semiconductor channel” the same or different than the “ two or more semiconductor channel layers” in line 3? For the purpose of examination, “two or more semiconductor channel” will be interpreted as“ two or more semiconductor channel layers”.
Claims 22-31 depend on claim 21 and inherit it’s deficiencies.
Claim 25 presently recites the limitation of “the method of claim 24, wherein the first sidewall section, the second sidewall section, and the central section are rounded sections”. How can the first sidewall section, the second sidewall section, and the central section be rounded sections if, as define in claim 24, the first sidewall section, the second sidewall section, and the central section are linear sections? For the purpose of examination, “the method of claim 24, wherein the first sidewall section, the second sidewall section, and the central section are rounded sections” will be interpreted as “the method of claim 23, wherein the first sidewall section, the second sidewall section, and the central section are rounded sections”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 16, 20 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16-17 and 20 of copending Application No. 18/405,146. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 16, claim 16 of copending Application No. 18/405,146 recites a method, comprising:
forming a semiconductor fin on a top surface of a semiconductor substrate, wherein the semiconductor fin comprises first semiconductor layers and second semiconductor layers alternately arranged;
forming a recess through the semiconductor fin and into the semiconductor substrate;
and
growing an epitaxial source/drain region over the buried epitaxial layer, wherein a bottom surface of the epitaxial source/drain region is below the top surface of the semiconductor substrate.
Claim 16 of copending Application No. 18/405,146 does not recite forming a buried epitaxial layer in the recess, wherein a top surface of the buried epitaxial layer is below the top surface of the semiconductor substrate.
Claim 17 of copending Application No. 18/405,146 recites forming a buried epitaxial layer in the recess, wherein a top surface of the buried epitaxial layer is below the top surface of the semiconductor substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the combination of claims 16 and 17 copending Application No. 18/405,146 recite claim 16 of the instant case.
Claims 16 and 17 of copending Application No. 18/405,146 do not recite a top surface of the buried epitaxial layer is below the top surface of the semiconductor substrate.
Claim 20 of copending Application No. 18/405,146 recites a top surface of the buried epitaxial layer is below the top surface of the semiconductor substrate
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the combination of claims 16, 17 and 20 of copending Application No. 18/405,146 recite claim 16 of the instant case.
Regarding claim 16, claim 16 of copending Application No. 18/405,146 recites the method of claim 16, further comprising forming a bottom dielectric layer over the buried epitaxial layer, wherein a top surface of the bottom dielectric layer is disposed below the top surface of the semiconductor substrate.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 21 and 32 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 30 of copending Application No. 18/405,146 in view of Kim et al. (US 2022/0399331 A1).
Regarding claim 21, claim 30 of copending Application No. 18/405,146 recites a method, comprising:
a fin structure over a top surface of a semiconductor substrate, wherein the fin structure comprises two or more semiconductor channel layers;
recess etching the fin structure;
forming inner spacers between the two or more semiconductor layers;
forming a buried epitaxial layer below the top surface of the semiconductor substrate; and
forming an epitaxial source/drain region connected to the two or more semiconductor channel layers, wherein the epitaxial source/drain region includes a sidewall connected to the two or more semiconductor channel and a bottom surface of extending below the top surface of the semiconductor substrate.
Claim 30 of copending Application No. 18/405,146 does not recite forming a sacrificial gate structure over the fin structure.
Kim teaches a method(Fig. 33, 5-12), comprising forming a sacrificial gate structure(162, ¶0082) over the fin structure(102a,103a, ¶0081). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of copending Application No. 18/405,146, to include forming a sacrificial gate structure over the fin structure, as taught by Kim, in order to use the sacrificial gate structure as a mask for etching the fin structure(¶0084).
Regarding claim 32, claim 30 of copending Application No. 18/405,146 recites a method, comprising:
forming two or more semiconductor channel layers vertically stacked with two or more sacrificial layers over a top surface of a semiconductor substrate;
forming a fin structure over and in the semiconductor substrate, wherein the fin structure comprises the two or more semiconductor channel layers and the two or more sacrificial layers, and a portion of the semiconductor substrate;
forming a sacrificial gate structure over the fin structure;
recess etching the fin structure, wherein the recess extends below the top surface of the semiconductor substrate; and
forming an epitaxial source/drain region in the recess, wherein the epitaxial source/drain region comprises:
growing a first epitaxial source/drain layer from the two or more semiconductor channel layers; and
growing a bulk epitaxial source/drain layer from the first epitaxial source/drain layer, wherein a bottom surface of the epitaxial source/drain region extends below the top surface of the semiconductor substrate.
Claim 30 of copending Application No. 18/405,146 does not forming a sacrificial gate structure over the fin structure;
recess etching the fin structure to form a recess outside the sacrificial gate structure.
Kim teaches a method(Fig. 33, 5-12), comprising forming a sacrificial gate structure(162, ¶0082) over the fin structure(102a,103a, ¶0081), recess etching(¶0084) the fin structure(102a,103a, ¶0081) to form a recess outside the sacrificial gate structure(162, ¶0082). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of copending Application No. 18/405,146, to include forming a sacrificial gate structure over the fin structure, recess etching the fin structure to form a recess outside the sacrificial gate structure, as taught by Kim, in order to use the sacrificial gate structure as a mask for etching the fin structure(¶0084).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16-17, 20-21, 23 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2022/0399331 A1).
Regarding claim 16, Kim teaches a method(Fig. 33, 5-12), comprising:
forming a semiconductor fin(102a,103a, ¶0081) on a top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28), wherein the semiconductor fin(102a,103a, ¶0081) comprises first semiconductor layers(102a, ¶0081) and second semiconductor layers(102b, ¶0081) alternately arranged(¶0081);
forming(Fig. 6) a recess through the semiconductor fin(102a,103a, ¶0081) and into the semiconductor substrate(101, ¶0027-28);
forming a buried epitaxial layer(EP1, ¶0132) in the recess, wherein a top surface of the buried epitaxial layer(EP1, ¶0132) is below the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28); and
growing an epitaxial source/drain region(EP2, ¶0132) over the buried epitaxial layer(EP1, ¶0132), wherein a bottom surface of the epitaxial source/drain region(EP2, ¶0132) is below the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28).
Regarding claim 17, Kim teaches the method of claim 16, wherein growing the buried epitaxial layer(EP1, ¶0132) comprises:
growing a conformal layer(180a, ¶0086) in the recess; and
growing a bottom-up layer(EP1, ¶0132) over the conformal layer(180a, ¶0086).
Regarding claim 20, Kim teaches the method of claim 16, further comprising forming a bottom dielectric layer(SP2, ¶0145, ¶0096) over the buried epitaxial layer(EP1, ¶0132), wherein a top surface of the bottom dielectric layer(SP2, ¶0145, ¶0096) is disposed below the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28).
Regarding claim 21, Kim teaches a method(Fig. 33, 5-12), comprising:
a fin structure(102a,103a, ¶0081) over a top surface of a semiconductor substrate(101, ¶0027-28), wherein the fin structure(102a,103a, ¶0081) comprises two or more semiconductor channel layers(CH2-CH4, ¶0042);
forming a sacrificial gate structure(162, ¶0082) over the fin structure(102a,103a, ¶0081);
recess etching(¶0084) the fin structure(102a,103a, ¶0081);
forming inner spacers(SP1, 182, 183, ¶0130) between the two or more semiconductor channel layers(CH2-CH4, ¶0042);
forming a buried epitaxial layer(EP1, ¶0132) below the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28); and
forming an epitaxial source/drain region(EP2, ¶0132) connected to the two or more semiconductor channel layers(CH2-CH4, ¶0042), wherein the epitaxial source/drain region(EP2, ¶0132) includes a sidewall connected to the two or more semiconductor channel layers(CH2-CH4, ¶0042) and a bottom surface of extending below the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28).
Regarding claim 23, Kim teaches the method of claim 21, wherein the bottom surface of the epitaxial source/drain region(EP2, ¶0132) comprises:
a first sidewall section(left sloping bottom sidewall);
a second sidewall section(right sloping bottom sidewall); and
a central section(center bottom section) connected to the first and second sidewall section(left and right sloping bottom sidewall)
wherein the first and second sidewall sections(left and right sloping bottom sidewall)
slopes downwards(Fig. 33).
Regarding claim 25, Kim teaches the method of claim 23, wherein the first sidewall section(left sloping bottom sidewall), the second sidewall section(right sloping bottom sidewall), and the central section(center bottom section) are rounded sections(Fig. 33).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 22, 24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0399331 A1) in view of Lin et al. (US 2025/0022957 A1).
Regarding claim 22, Kim teaches the method of claim 21, but is not relied on to teach the bottom surface of the epitaxial source/drain region(EP2, ¶0132) extends below the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28) in a range between about 5 nm and about 20 nm.
Lin teaches a method(Figs. 1-22) wherein the bottom surface of the epitaxial source/drain region(246, ¶0037) extends(H2) below the top surface of the semiconductor substrate(202, ¶0017) in a range between about 5 nm and about 20 nm(¶0037). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim, so that the bottom surface of the epitaxial source/drain region extends below the top surface of the semiconductor substrate in a range between about 5 nm and about 20 nm, as taught by Lin, to ensure a sufficiently large volume of the source/drain features(¶0031).
Regarding claim 24, Kim teaches the method of claim 23, but is not relied on to teach the first sidewall section(left sloping bottom sidewall), the second sidewall section(right sloping bottom sidewall), and the central section(center bottom section) are linear sections.
Lin teaches a method(Figs. 24a) wherein the first sidewall section, the second sidewall section, and the central section are linear sections(Fig. 24A). t It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim, so that the first sidewall section, the second sidewall section, and the central section are linear sections, as taught by Lin, to ensure a sufficiently large volume of the source/drain features(¶0031).
Regarding claim 26, Kim teaches the method of claim 24, but is not relied on to teach the first sidewall section and the central section form an angle in a range between 120° and 180°.
Lin teaches a method(Figs. 24a) wherein the first sidewall section and the central section form an angle in a range between 120° and 180°(¶0053). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim, so that the first sidewall section, the second sidewall section, and the central section are linear sections, as taught by Lin, to ensure a sufficiently large volume of the source/drain features(¶0031).
Claims 27-35 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0399331 A1) in view of More (US 2022/0059703 A1)
Regarding claim 27, Kim teaches the method of claim 21, but is not relied on to teach forming the epitaxial source/drain region(EP2, ¶0132) comprises:
growing a first epitaxial source/drain layer from the two or more semiconductor channel layers(CH2-CH4, ¶0042); and
growing a bulk epitaxial source/drain layer from the first epitaxial source/drain layer.
More teaches a method(Fig. 19) wherein forming the epitaxial source/drain region(50-1, 50-2, ¶0090) comprises: growing a first epitaxial source/drain layer(50-1, ¶0085) from the two or more semiconductor channel layers(25, ¶0085); and growing a bulk epitaxial source/drain layer(50-2, ¶0091) from the first epitaxial source/drain layer(50-1, ¶0085). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim, so that forming the epitaxial source/drain region comprises: growing a first epitaxial source/drain layer from the two or more semiconductor channel layers; and growing a bulk epitaxial source/drain layer from the first epitaxial source/drain layer, as taught by More, in order to have source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents(abstract).
Regarding claim 28, Kim teaches the method of claim 27, further comprising forming a bottom dielectric layer(SP2, ¶0145, ¶0096) on the buried epitaxial layer(EP1, ¶0132).
Regarding claim 29, Kim teaches the method of claim 28, further comprising forming an opening through the bottom dielectric layer(SP2, ¶0145, ¶0096) to expose a portion of the buried epitaxial layer(EP1, ¶0132).
Regarding claim 30, Kim teaches the method of claim 29, but is not relied on to teach growing the first epitaxial source/drain layer comprises growing the first epitaxial source/drain layer from exposed portion of the buried epitaxial layer(EP1, ¶0132).
More teaches a method(Fig. 19) wherein growing the first epitaxial source/drain layer(50-1, ¶0085) comprises growing the first epitaxial source/drain layer(50-1, ¶0085) from exposed portion of the buried epitaxial layer(49, ¶0088). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim, so that growing the first epitaxial source/drain layer comprises growing the first epitaxial source/drain layer from exposed portion of the buried epitaxial layer, as taught by More, in order to have source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents(abstract).
Regarding claim 31, Kim teaches the method of claim 21, wherein the epitaxial source/drain region(EP2, ¶0132) has a first width(width between CH2) above the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28) and a second width(width contacting EP1) below the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28).
Kim is not relied on to teach the second width(width contacting EP1) is greater than the first width(width between CH2).
More teaches a method(Fig. 20) wherein the second width(width of 50-2 contacting 49) is greater(Fig. 20) than the first width(width of 50-2 between channel 25). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim, so that the second width(width contacting EP1) is greater than the first width, as taught by More, in order to have source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents(abstract).
Regarding claim 32, Kim teaches a method(Fig. 33, 5-12), comprising:
forming two or more semiconductor channel layers(CH2-CH4, ¶0042) vertically stacked with two or more sacrificial layers(102a, ¶0081) over a top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28);
forming a fin structure(102a,103a, ¶0081) over and in the semiconductor substrate(101, ¶0027-28), wherein the fin structure(102a,103a, ¶0081) comprises the two or more semiconductor channel layers(CH2-CH4, ¶0042) and the two or more sacrificial layers(102a, ¶0081), and a portion of the semiconductor substrate(101, ¶0027-28);
forming a sacrificial gate structure(162, ¶0082) over the fin structure(102a,103a, ¶0081);
recess etching(¶0084) the fin structure(102a,103a, ¶0081) to form a recess outside the sacrificial gate structure(162, ¶0082), wherein the recess extends below the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28); and
forming an epitaxial source/drain region(EP2, ¶0132) in the recess,
wherein a bottom surface of the epitaxial source/drain region(EP2, ¶0132) extends below the top surface(top of CH1) of the semiconductor substrate(101, ¶0027-28).
Kim is not relied on to teach the epitaxial source/drain region(EP2, ¶0132) comprises:
growing a first epitaxial source/drain layer from the two or more semiconductor channel layers(CH2-CH4, ¶0042); and
growing a bulk epitaxial source/drain layer from the first epitaxial source/drain layer.
More teaches a method(Fig. 19) wherein forming the epitaxial source/drain region(50-1, 50-2, ¶0090) comprises: growing a first epitaxial source/drain layer(50-1, ¶0085) from the two or more semiconductor channel layers(25, ¶0085); and growing a bulk epitaxial source/drain layer(50-2, ¶0091) from the first epitaxial source/drain layer(50-1, ¶0085). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kim, so that forming the epitaxial source/drain region comprises: growing a first epitaxial source/drain layer from the two or more semiconductor channel layers; and growing a bulk epitaxial source/drain layer from the first epitaxial source/drain layer, as taught by More, in order to have source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents(abstract).
Regarding claim 33, Kim teaches the method of claim 32, further comprising:
forming a buried epitaxial layer(EP1, ¶0132) in the recess prior to forming the epitaxial source/drain region(EP2, ¶0132).
Regarding claim 34, Kim teaches the method of claim 33, further comprising forming a bottom dielectric layer(SP2, ¶0145, ¶0096) on the buried epitaxial layer(EP1, ¶0132), wherein the bottom dielectric layer(SP2, ¶0145, ¶0096) partially covers the buried epitaxial layer(EP1, ¶0132).
Regarding claim 35, Kim, in view of More, teaches the method of claim 34, further comprising:
forming an opening through the bottom dielectric layer(SP2, ¶0145, ¶0096), and a portion of the first epitaxial source/drain layer(EP2, ¶0132) is in contact with the bottom dielectric layer(SP2, ¶0145, ¶0096).
Allowable Subject Matter
Claims 18-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 18, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “selectively etching back sidewalls of the semiconductor substrate between the top surface of the semiconductor substrate and a top surface of the buried epitaxial layer”.
Claim 19 depend on claim 18 and inherits it allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cheng et al. (US 2025/0081520 A1) Discloses a method.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892
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