DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Group III, species (1), claims 18-20 and new claims 21-37, in the reply filed on 5/18/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant’s cancellation of non-elected claims 1-17 is acknowledged.
Claim Objections
Claim 18 is objected to because of the following informalities: Replace “wherein the mask comprising” with –wherein the mask comprises—to address a grammatical issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 33 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 33, the follow limitation is indefinite:
wherein a spacing between the at least one main feature and another main feature adjacent to the at least one main feature is the same as a spacing between the at least one assist pattern on the at least one main feature and another assist pattern on the another main feature.
Referring to Applicant’s fig. 4, the same spacing refers to y/x~1.0. Claim 33 recites the spacing x between at least one main feature (e.g. top left) and another main feature (e.g. top right). However, in claim 33 the spacing between the assist patterns is not the distance y. To meet the relationship y/x~1.0 the spacing amongst three main features is need, rather than two main features as recited in claim 33.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18, 19, 21-26, 28-32 and 34-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US Publication No. 2015/0091127 A1 in view of Wang et al., US Publication No. 2018/0335703 A1.
Lee teaches:
18. A method for fabricating a semiconductor wafer, comprising: (see figs. 13-15) patterning a semiconductor substrate (102) by using a mask (106) to form a trench (132, 136) in the semiconductor substrate,…
filling a dielectric material (140) into the trench to form an isolation structure. See Lee at para. [0123] – [0133].
Lee does not expressly teach:
wherein the mask comprising:
at least one main feature comprising a plurality of sidewalls intersecting to define distal corners; and
assist patterns formed on the distal corners, wherein a number of the assist patterns is less than a number of the distal corners;
In an analogous art, Wang teaches:
(see figs. 5c and 8c) wherein the mask comprising:
at least one main feature (32) comprising a plurality of sidewalls intersecting to define distal corners; and
assist patterns (34) formed on the distal corners, wherein a number of the assist patterns (e.g. two) is less than a number of the distal corners (e.g. four). See Wang at para. [0017] – [0022], para. [0028] – [0031].
Lee further teaches:
19. The method of claim 18, further comprising forming semiconductor devices in the semiconductor substate after filling the dielectric material into the trench (e.g. forming cell transistors at para. [0136])
Wang further teaches:
21. The method of claim 18, wherein the at least one main feature (32) comprises four distal corners, and the number of the assist patterns (34) is two, figs. 5c and 8c.
22. The method of claim 18, wherein the at least one main feature (32) comprises at least two assist patterns (34), and the assist patterns are formed at the alternating distal corners of the at least one main feature, figs. 5c and 8c.
23. The method of claim 18, wherein the at least one main feature (32) comprises at least two assist patterns (34), and the assist patterns are unconnected to each other along a same sidewall among the plurality of sidewalls of the at least one main feature, figs. 5c and 8c.
Lee further teaches:
24. The method of claim 18, wherein the isolation structure (132) comprises a mesh- shaped isolation structure (e.g. mesh shape in figs. 15A-15B)
Lee teaches:
25. A method for fabricating a semiconductor wafer, comprising: (see figs. 12-15) providing a mask (106) having at least one main feature (e.g. corresponding to active region 134),
forming a pattern (104) on a semiconductor substrate (102) using the mask; and
forming an isolation structure (132, 136- 140) in the semiconductor substrate using the pattern. See Lee at para. [0123] – [0133].
Lee does not expressly teach:
the main feature comprising:
a plurality of edges interconnecting a plurality of corners, wherein at least one edge among the plurality of edges extends between a pair of adjacent corners of the plurality of corners; and
at least one assist pattern on a corner among the plurality of corners, wherein a number of the assist patterns is less than a number of the plurality of edges of the at least one main feature; and
In an analogous art, Wang teaches:
(see figs. 5c and 8c) providing a mask having at least one main feature (32), the main feature comprising:
a plurality of edges (e.g. of 32) interconnecting a plurality of corners, wherein at least one edge among the plurality of edges extends between a pair of adjacent corners of the plurality of corners; and
at least one assist pattern (34) on a corner among the plurality of corners, wherein a number of the assist patterns (e.g. two) is less than a number of the plurality of edges (e.g. four) of the at least one main feature. See Wang at para. [0017] – [0022], para. [0028] – [0031].
Lee further teaches:
26. The method of claim 25, further comprising:
etching the semiconductor substrate (102) guided by the pattern (104) to form trenches (132, 136) in the semiconductor substrate; and
filling an isolation material (140) into the trenches to form the isolation structure, para. [0123] – [0133], figs. 13-15.
Wang further teaches:
28. The method of claim 25, wherein the at least one main feature (32) comprises a polygon, selected from a group consisting of a square, a rectangle, a rhombus, and a hexagon, figs. 5c and 8c.
29. The method of claim 25, wherein the at least one assist pattern (34) has a symmetrical cross-sectional profile selected from the group consisting of a square-shaped, a rectangular-shaped, a spherical shaped, and an ellipse-shaped cross-sectional profile, figs. 5c and 8c.
30. The method of claim 25, wherein the at least one main feature (32) comprises two assist patterns (34), and the assist patterns are arranged along a diagonal axis to a linear axis of the at least one main feature, figs. 5c and 8c.
31. The method of claim 25, wherein the at least one main feature (32) comprises two assist patterns (34), and the assist patterns and a center point of the at least one main feature are arranged along a straight line (e.g. diagonal line), figs. 5c and 8c.
32. The method of claim 25, wherein the at least one main feature (32) comprises two assist patterns (34), and the assist patterns are arranged on alternating corners of the plurality of corners, figs. 5c and 8c.
Lee teaches:
34. A method for fabricating a semiconductor wafer, comprising (see figs. 13-15):
providing a mask (106) having at least one main feature (e.g. corresponding to active region 134),
patterning a semiconductor substrate (102) by using the mask (106) to form a recess (132, 136) extending into the semiconductor substrate; and
filling the recess with a dielectric material (140) to form an isolation structure. See Lee at para. [0123] – [0133].
Lee does not expressly teach:
the main feature comprising: a first assist pattern and a second assist pattern partially overlapping the at least one main feature, wherein the first assist pattern and the second assist pattern are diametrically opposed to each other about a center of the at least one main feature;
Wang teaches:
(see figs. 5c and 8c) providing a mask having at least one main feature (32), the main feature comprising: a first assist pattern (34a) and a second assist pattern (34b) partially overlapping the at least one main feature (32), wherein the first assist pattern (34a) and the second assist pattern (34b) are diametrically opposed to each other about a center of the at least one main feature; See Wang at para. [0017] – [0022], para. [0028] – [0031].
Wang also teaches:
(see fig. 2) providing a mask having at least one main feature (22), the main feature comprising: a first assist pattern (24) and a second assist pattern (another 24 located at diagonal) partially overlapping the at least one main feature (22), wherein the first assist pattern (24) and the second assist pattern (another 24 located at diagonal) are diametrically opposed to each other about a center of the at least one main feature; See Wang at para. [0005].
Wang further teaches:
35. The method of claim 34, wherein the at least one main feature (32) comprises a plurality of edges interconnecting a plurality of corners, and the first assist pattern (34a) and the second assist pattern (34b) at least partially overlaps the plurality of corners, figs. 5c and 8c. Wang also teaches this limitation in fig. 2.
36. The method of claim 35, wherein the first assist pattern (34a) is spaced apart from the second assist pattern (34b) by at least one corner among the plurality of corners, figs. 5c and 8c. Wang also teaches this limitation in fig. 2 if the assist patterns are located at a diagonal.
37. The method of claim 35, wherein the first assist pattern (34a) and the second assist pattern (34b)are disposed at a first corner and a second corner of the plurality of corners, and the first corner and the second corner are not interconnected by a common edge among the plurality of edges, figs. 5c and 8c. Wang also teaches this limitation in fig. 2 if the assist patterns are located at a diagonal.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lee with the teachings of Wang because the assist patterns can prevent corner rounding problems. See Wang at para. [0001].
Claim(s) 20 s/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Wang, as applied to claim 18 above, in further view of Koshimizu et al., US Publication No. 2024/0421166 A1.
Regarding claim 20:
Lee and Wang teach all the limitations of clam 18 above, but do not expressly teach:
further comprising forming an interconnect structure on the semiconductor substrate and the isolation structure.
In an analogous art, Koshimizu teaches:
(see fig. 16) further comprising forming an interconnect structure (M1, M2, IL1, IL2) on the semiconductor substrate (SUB) and the isolation structure (3a, 3b), para. [0104] – [0112].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lee with the teachings of Koshimizu in order to form wiring that can connect to the gate, source and drain of the transistor. See Koshimizu at para. [0108] – [0110].
Claim(s) 25, 27, 28 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US Publication No. 2015/0091127 A1 in view of Cho, US Publication No. 2010/0092875 A1.
Lee teaches:
25. A method for fabricating a semiconductor wafer, comprising: (see figs. 12-15) providing a mask (106) having at least one main feature (e.g. corresponding to active region 134),
forming a pattern (104) on a semiconductor substrate (102) using the mask; and
forming an isolation structure (132, 136- 140) in the semiconductor substrate using the pattern. See Lee at para. [0123] – [0133].
Lee does not expressly teach:
the main feature comprising:
a plurality of edges interconnecting a plurality of corners, wherein at least one edge among the plurality of edges extends between a pair of adjacent corners of the plurality of corners;
at least one assist pattern on a corner among the plurality of corners, wherein a number of the assist patterns is less than a number of the plurality of edges of the at least one main feature; and
In an analogous art, Cho teaches (see figs. 3C and 4A):
the main feature (400 in fig. 4A; and 300, 340, 350, 360 in fig .3C) comprising:
a plurality of edges interconnecting a plurality of corners, wherein at least one edge among the plurality of edges extends between a pair of adjacent corners of the plurality of corners; and
at least one assist pattern (e.g. comprising 322, 324) on a corner among the plurality of corners, wherein a number of the assist patterns (e.g. interpreted as one assist pattern or two serifs 322, 324) is less than a number of the plurality of edges (e.g. four edges) of the at least one main feature; See Cho at para. [0029] – [0039].
Lee further teaches:
27. The method of claim 26, further comprising: planarizing (e.g. see CMP at para. [0152] – [0153]) the isolation material to form the isolation structure (140) and exposing a top surface of the semiconductor substrate (102), wherein the top surface of the semiconductor substrate (102) is flush with a top surface of the isolation structure (140), fig. 16.
Cho further teaches:
28. The method of claim 25, wherein the at least one main feature (400 in fig. 4A; and 300, 340, 350, 360 in fig .3C) comprises a polygon, selected from a group consisting of a square, a rectangle, a rhombus, and a hexagon.
Cho further teaches:
33. The method of claim 25, (see fig. 3C annotated below) wherein a spacing (X) between the at least one main feature and another main feature adjacent to the at least one main feature is the same as a spacing (Y) between the at least one assist pattern on the at least one main feature and another assist pattern on the another main feature (e.g. substantially the same X ~ Y). Also see the 35 USC 112 rejection above.
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It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lee with the teachings of Cho to obtain unform corners and uniform overlap margins. See Cho at para. [0012], [0016].
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Fujimara, US 20100058282 A1 (e.g. In fig. 8 Fujimara teaches mask patterns with assist patterns.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
17 July 2026
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