DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9, and 21 have been considered but are not persuasive. The rejection using prior art Choi ‘851 is maintained. Upon further consideration, the examiner has identified the first insulating layer and conductive via within the recited limitations in a new way as set forth below. .
Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-17, 21 and 23-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claims 1, 9 and 21 there is lack of antecedent basis for “the conductive via”.
Claims 2-8, 10-17 and 23-24 inherit the deficiencies of claims 1, 9 and 21 from which they depend.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8, 10, 12-14, 16, and 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2020/0402903 A1), hereafter “Chen ‘903”, further in view of Choi (US 2022/0254756 A1), hereafter “Choi ‘756”, further in view of Chen et al. (US 2020/0402951 A1), hereafter “Chen ‘951”, and further in view of Choi et al. (US 2022/0375851 A1), hereafter “Choi ‘851”.
As to claim 1, Chen ‘903 teaches a semiconductor device comprising:
a first semiconductor die (⁋ [0026], 12, Fig.3) comprising a single conductive via (⁋ [0026], 25, Fig.3), a first capacitor (⁋ [0026], 131-1, Fig.3) and a second capacitor (⁋ [0026], 131-2, Fig.3), wherein the conductive via (25) and the second capacitor (131-2) are electrically connected with the first capacitor (131-1) (⁋ [0039], Fig. 13, 13b); and
a second semiconductor die (⁋⁋ [0026], [0029], 10, Fig.1) in contact with the first semiconductor die, wherein the first semiconductor die (12) and the second semiconductor die (10) are arranged along a first direction (vertical, Fig. 1).
Chen ‘903 fails to teach the first capacitor and the second capacitor are embedded in a first insulation layer, and the conductive via penetrates the first insulation layer and extends to a second insulation layer, wherein the conductive via comprises a backside through silicon via (BTSV) extending toward a substrate of the semiconductor device; and the second semiconductor die comprising a diode, the diode is configured to direct electrons accumulated at the first capacitor to a ground, and a depth of the first capacitor is smaller than a length of the conductive via, wherein a thickness of the first insulation layer is smaller than a depth of the conductive via.
Choi ‘756 teaches a similar stacked die arrangement (⁋ [0077], 430, Fig. 4) having a diode (⁋⁋ [0070], [0084], D). The combination of Chen ‘903 and Choi ‘756 therefore teaches the second semiconductor die having a diode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the diode as taught by Choi ‘756 into the stacked die structure as taught by Chen ‘903 in order to yield the predictable result of controlling current. A person of ordinary skill would have been motivated to do so, with a reasonable expectation of success, because of diodes are well-known devices for current control as taught by Choi ‘756.
Chen ‘903 and Choi ‘756 fails to teach the first capacitor and the second capacitor are embedded in a first insulation layer, and the conductive via penetrates the first insulation layer and extends to a second insulation layer, wherein the conductive via comprises a backside through silicon via (BTSV) extending toward a substrate of the semiconductor device; and a depth of the first capacitor is smaller than a length of the conductive via, wherein a thickness of the first insulation layer is smaller than a depth of the conductive via.
. Chen ‘951 teaches a similar stacked die structure with a capacitor (⁋ [0043], 41, Fig. 6) and conductive via (⁋ {0038], 216, Fig. 6) where the depth of the capacitor is smaller than a length of the conductive via.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the size difference of the capacitor and conductive via as taught in Chen ‘951 into the semiconductor device of Chen ‘903 and Choi ‘756 as one would look to the structural design of a known trench capacitor made in a semiconductor capacitor of Chen ‘951 in order to provide the improved interconnection or capacitance.
Chen ‘903, Choi ‘756, and Chen ‘951 fails to teach the first capacitor and the second capacitor are embedded in a first insulation layer, and the conductive via penetrates the first insulation layer and extends to a second insulation layer, wherein the conductive via comprises a backside through silicon via (BTSV) extending toward a substrate of the semiconductor device; and wherein a thickness of the first insulation layer is smaller than a depth of the conductive via.
Choi ‘851 teaches also teaches a deep trench capacitor in a die wherein a first capacitor (⁋ [0025], right 302, Fig. 3) and a second capacitor (second from right 302) are embedded in a first insulation layer (⁋ [0026], ILM layer, Figs. 6A-6D show where the ILM layer begins and ends), and the conductive via (⁋⁋ [0025]-[0026], 324, see annotated Fig. 3 below) penetrates the first insulation layer (annotated Fig. 3), extends to a second insulation layer (⁋ [0025], 316), comprising a via that extends to the substrate (⁋ [0026]), and wherein a thickness of the first insulation layer (ILM) is smaller than a depth of the conductive via (324).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the first and second insulation layer as taught by Choi ‘851 into the semiconductor device of Chen ‘903, Choi ‘756, and Chen ‘951 to reduce voltage drop and spikes in a plurality of circuits (⁋ [0025]). This also solves for the problem of the DTCs occupying volume in the ILD (second insulating layer) that would otherwise be available for routing the horizontal metal traces (⁋ [0024]).
Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the conductive via penetrating the first insulation layer and extending to the second insulation layer as taught by Choi ‘851 included in the design of Chen ‘903, Choi ‘756, and Chen ‘951 to allow the via to act as an interconnect to the plurality of circuits while also being separated from each other by an ILD (second insulating layer) (⁋ [0025]).
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As to claim 2, Chen ‘903 teaches wherein the first semiconductor die (12) further comprises a first conductive contact (19-1/19-2), the second semiconductor die (10) further comprises a second conductive contact (18-1/18-2), and wherein the first semiconductor die and the second semiconductor die are directly connected through the first conductive contact and the second conductive contact (⁋ [0026], read on by “The first conductive pads 18-1, 18-2, 18-3, 18-4 may physically contact with the second conductive pads 19-1, 19-2, 19-3, 19-4 in one-on-one manner allowing signal transmission between the IC die 10 and the capacitor die 12”).
As to claim 3, Chen ‘903 teaches wherein the conductive via (25) is configured to receive a power signal (⁋ [0039]).
As to claim 4, Choi ‘756 teaches wherein the diode is configured to be reversely biased (⁋ [0072], Fig. 3B, read on by “reverse current is applied to the diode”).
As to claim 5, Choi ‘756 teaches wherein the diode (D) comprises a cathode electrically connected to the first capacitor (⁋ [0084], Fig. 4, output terminal of diode connected to the inductor which is connected to a node that the capacitor is also connected to) and an anode electrically connected to the ground (⁋ [0084], read on by “An input terminal of the diode 434 may be electrically connected to a ground”).
As to claim 6, Choi ‘851 teaches wherein the first capacitor (right 302, Fig. 3) is encapsulated within the first insulation layer (⁋ 0026], see annotated Fig. 3) of the first semiconductor die (Chen ‘903, 12) extending along a second direction (left to right) vertical to the first direction (vertical), and the depth of the first capacitor is smaller than a thickness of the first insulation layer (annotated Fig. 3 shows first insulation layer thicker than 302).
As to claim 8, Chen ‘903 teaches wherein the first capacitor (131-1) is arranged between the conductive via (25) and the second capacitor (131-2) (Fig. 3).
As to claim 10, Chen ‘903, Chen ‘951, and Choi ‘851 fails to teach further comprising: a diode embedded within the second semiconductor die for directing the electrons accumulated at the first capacitor to a ground.
Choi ‘756 teaches a similar stacked die arrangement (⁋ [0077], 430, Fig. 4) having a diode (⁋⁋ [0070], [0084], D). The combination of Chen ‘903 and Choi ‘756 therefore teaches the second semiconductor die having a diode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the diode as taught by Choi ‘756 into the stacked die structure as taught by Chen ‘903 in order to yield the predictable result of controlling current. A person of ordinary skill would have been motivated to do so, with a reasonable expectation of success, because of diodes are well-known devices for current control as taught by Choi ‘756.
As to claim 12, Choi ‘756 teaches wherein the diode is configured to be reversely biased (⁋ [0072], Fig. 3B, read on by “reverse current is applied to the diode”).
As to claim 13, Choi ‘756 teaches wherein the diode (D) comprises a cathode electrically connected to the first capacitor (⁋ [0084], Fig. 4, output terminal of diode connected to the inductor which is connected to a node that the capacitor is also connected to) and an anode electrically connected to the ground (⁋ [0084], read on by “An input terminal of the diode 434 may be electrically connected to a ground”.
As to claim 14, Chen ‘903 teaches wherein the first capacitor and the second capacitor are deep trench capacitors (DTC) (⁋ [0026]).
As to claim 16, Chen ‘903, Chen ‘951, Choi ‘756, and Choi ‘851 does not teach wherein distance between the first capacitor and the second capacitor is greater than 5 um.
On the other hand, the Examiner notes Applicant has not specified a criticality to the dimensions.
Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions or variable are critical. "The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. . . . In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range." In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
As to claim 23, Chen ‘903, Choi ‘756, and Choi ‘851 fail to teach wherein a length of the conductive via is greater than a depth of the first capacitor.
Chen ‘951 teaches a similar stacked die structure with a capacitor (⁋ [0043], 41, Fig. 6) and conductive via (⁋ {0038], 216, Fig. 6) where the depth of the capacitor is smaller than a length of the conductive via.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the size difference of the capacitor and conductive via as taught in Chen ‘951 into the semiconductor device of Chen ‘903 and Choi ‘756 as one would look to the structural design of a known trench capacitor made in a semiconductor capacitor of secondary ref in order to provide the improved interconnection or capacitance.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘903, Choi ‘756, Chen ‘951, and Choi ‘851 and further in view of Hosogai et al. (US 2022/0028782 A1), hereafter “Hosogai”.
As to claim 7, Chen ‘903, Choi ‘756, Chen ‘951, and Choi ‘851 fail to teach wherein a distance between the first capacitor and the second capacitor is smaller than the depth of the first capacitor and a depth of the second capacitor.
Hosogai teaches a similar semiconductor device also containing trench capacitors (⁋ [0026], 3, Fig. 1) wherein the distance between the capacitors (⁋ [0027], “a distance between the trench capacitors 3, may be in a range of 1 micrometer to 3 micrometer”) is smaller than the depth of the capacitors (⁋ [0027], “the depth of the trench capacitor 3 may be in a range of 5 micrometer to 20 micrometer”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the depth and distances of adjacent trench capacitors as taught by Hosogai with the semiconductor device of Chen ‘903, Choi ‘756, Chen ‘951, and Choi ‘851 in order to increase the surface area of the capacitor while overall saving space and increasing device density.
Claim 9, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen’ 903, Chen ‘951, and Choi ‘851.
As to claim 9, Chen ‘903 teaches a semiconductor device comprising:
a first semiconductor die (⁋ [0026], 12, Fig.3);
a first capacitor embedded within the first semiconductor die (⁋ [0026], 131-2, Fig.3);
a single conductive via (⁋ [0026], 25, Fig.3) adjacent the first capacitor and electrically connected with the first capacitor (⁋ [0039], Fig. 13, 13b);
a second capacitor (⁋ [0026], 131-2, Fig.3) embedded within the first semiconductor die and electrically connected with the first capacitor (⁋ [0039], Fig. 13, 13b); and
a second semiconductor die (⁋⁋ [0026], [0029], 10, Fig.1) comprising a processing unit (⁋ [0042], 11, Fig. 1) configured to receive a power signal from a power line (⁋⁋ [0041], [0042], PD, Fig. 13), wherein the first semiconductor die is stacked on the second semiconductor die along a first direction (vertical, Fig. 1), the first capacitor is electrically connected to the power line (PD) and configured to regulate the power signal (⁋ [0041]).
Chen ‘903 fails to teach wherein the first capacitor and the second capacitor are embedded in a first insulation layer, and the conductive via penetrates the first insulation layer and extends to a second insulation layer, wherein the conductive via comprises a backside through silicon via (BTSV) extending toward a substrate of the semiconductor device; and a length of the conductive via is greater than a depth of the first capacitor, wherein a thickness of the first insulation layer is smaller than a depth of the conductive via.
Chen ‘951 teaches a similar stacked die structure with a capacitor (⁋ [0043], 41, Fig. 6) and conductive via (⁋ {0038], 216, Fig. 6) where the depth of the capacitor is smaller than a length of the conductive via.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the size difference of the capacitor and conductive via as taught in Chen ‘951 into the semiconductor device of Chen ‘903 as one would look to the structural design of a known trench capacitor made in a semiconductor capacitor of Chen ‘951 in order to provide the improved interconnection or capacitance.
Chen ‘903 and Chen ‘951 fails to teach wherein the first capacitor and the second capacitor are embedded in a first insulation layer, and the conductive via penetrates the first insulation layer and extends to a second insulation layer, wherein the conductive via comprises a backside through silicon via (BTSV) extending toward a substrate of the semiconductor device; and wherein a thickness of the first insulation layer is smaller than a depth of the conductive via.
Choi ‘851 teaches also teaches a deep trench capacitor in a die wherein a first capacitor (⁋ [0025], right 302, Fig. 3) and a second capacitor (second from right 302) are embedded in a first insulation layer (⁋ [0026], ILM layer, Figs. 6A-6D show where the ILM layer begins and ends), and the conductive via (⁋⁋ [0025]-[0026], 324, see annotated Fig. 3 below) penetrates the first insulation layer (annotated Fig. 3), extends to a second insulation layer (⁋ [0025], 316), comprising a via that extends to the substrate (⁋ [0026]), and wherein a thickness of the first insulation layer (ILM) is smaller than a depth of the conductive via (324).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the first and second insulation layer as taught by Choi ‘851 into the semiconductor device of Chen ‘903, and Chen ‘951 to reduce voltage drop and spikes in a plurality of circuits (⁋ [0025]). This also solves for the problem of the DTCs occupying volume in the ILD (second insulating layer) that would otherwise be available for routing the horizontal metal traces (⁋ [0024]).
Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the conductive via penetrating the first insulation layer and extending to the second insulation layer as taught by Choi ‘851 included in the design of Chen ‘903, and Chen ‘951 to allow the via to act as an interconnect to the plurality of circuits while also being separated from each other by an ILD (second insulating layer) (⁋ [0025]).
As to claim 11, Choi ‘851 teaches wherein the first capacitor (⁋ [0025], right 302, Fig. 3) is encapsulated within the first insulation layer (⁋ 0026], see annotated Fig. 3) of the first semiconductor die (Chen ‘903, 12) extending along a second direction (left to right) vertical to the first direction (vertical).
As to claim 17, Chen ‘903 teaches the first capacitor (131-1) is arranged between the conductive via (25) and the second capacitor (131-2) (Fig. 3).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘903, Chen ‘951, Choi ‘851, and Choi ‘756, and further in view of Liu et al. (US 2022/0149047 A1), hereafter “Liu”.
As to claim 15, Chen ‘903, Chen ‘951, Choi ‘851, and Choi ‘756 fail to teach wherein depths of the first capacitor and the second capacitor are greater than 6 um.
Liu teaches a semiconductor structure containing a deep trench capacitor (⁋ [0090]) wherein the deep trench capacitor has a depth greater than 6 um (⁋ [0090], 10-20 microns).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the trench depth taught by Liu into the semiconductor structure taught by Chen ‘903, Chen ‘951, Choi ‘851, and Choi ‘756 to increase surface area of the capacitor and determine a depth based upon a capacitance required by the integrated circuit device.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘903, Choi ‘756, and Choi ‘851.
As to claim 21, Chen ‘903 teaches semiconductor device comprising:
a first semiconductor die (⁋ [0026], 12, Fig.1);
a first capacitor (⁋ [0026], 131-2, Fig.1) embedded within the first semiconductor die;
a second capacitor (⁋ [0026], 131-2, Fig.1) embedded within the first semiconductor die and electrically connected with the first capacitor;
a second semiconductor die (⁋ [0026], 10, Fig.1) comprising a processing unit (⁋ [0042], 11, Fig. 1) configured to receive a power signal from a power line (⁋⁋ [0041], [0042], PD, Fig. 13), wherein the first semiconductor die is stacked on the second semiconductor die along a first direction (vertical, Fig. 1), and the first capacitor is electrically connected to the power line (PD) and configured to regulate the power signal (⁋ [0041]);
a single conductive via (⁋ [0026], 25, Fig.3) adjacent the first capacitor and electrically connected with the first capacitor (⁋ [0039], Fig. 13, 13b);
Chen ‘903 fails to teach a diode embedded within the second semiconductor die for directing the electrons accumulated at the first capacitor to a ground; and wherein the first capacitor and the second capacitor are embedded in a first insulation layer, and the conductive via penetrates the first insulation layer and extends to a second insulation layer, wherein the conductive via comprises a backside through silicon via (BTSV) extending toward a substrate of the semiconductor device, wherein a thickness of the first insulation layer is smaller than a depth of the conductive via.
Choi ‘756 teaches a similar stacked die arrangement (Fig. 5) having a diode D. The combination of Chen ‘903 and Choi ‘756 therefore teaches the second semiconductor die having a diode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the diode as taught by Choi ‘756 into the stacked die structure as taught by Chen ‘903 in order to yield the predictable result of controlling current. A person of ordinary skill would have been motivated to do so, with a reasonable expectation of success, because of diodes are well-known devices for current control as taught by Choi ‘756.
Chen ‘903 and Choi ‘756 fails to teach wherein the first capacitor and the second capacitor are embedded in a first insulation layer, and the conductive via penetrates the first insulation layer and extends to a second insulation layer, wherein the conductive via comprises a backside through silicon via (BTSV) extending toward a substrate of the semiconductor device, wherein a thickness of the first insulation layer is smaller than a depth of the conductive via.
Choi ‘851 teaches also teaches a deep trench capacitor in a die wherein a first capacitor (⁋ [0025], right 302, Fig. 3) and a second capacitor (second from right 302) are embedded in a first insulation layer (⁋ [0026], ILM layer, Figs. 6A-6D show where the ILM layer begins and ends), and the conductive via (⁋⁋ [0025]-[0026], 324, see annotated Fig. 3 below) penetrates the first insulation layer (annotated Fig. 3), extends to a second insulation layer (⁋ [0025], 316), comprising a via that extends to the substrate (⁋ [0026]), and wherein a thickness of the first insulation layer (ILM) is smaller than a depth of the conductive via (324).
It would have been obvious to one of ordinary skill in the art before the effective filing date to include the first and second insulation layer as taught by Choi ‘851 into the semiconductor device of Chen ‘903, and Choi ‘756 to reduce voltage drop and spikes in a plurality of circuits (⁋ [0025]). This also solves for the problem of the DTCs occupying volume in the ILD (second insulating layer) that would otherwise be available for routing the horizontal metal traces (⁋ [0024]).
Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the conductive via penetrating the first insulation layer and extending to the second insulation layer as taught by Choi ‘851 included in the design of Chen ‘903, and Choi ‘756 to allow the via to act as an interconnect to the plurality of circuits while also being separated from each other by an ILD (second insulating layer) (⁋ [0025]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘903, Choi ‘756, Choi ‘851, and further in view of Hosogai.
As to claim 24, Chen ‘903, Choi ‘756, and Choi ‘851 fail to teach wherein a distance between the first capacitor and the second capacitor is smaller than a depth of the first capacitor.
Hosogai teaches a similar semiconductor device also containing trench capacitors (⁋ [0026], 3, Fig. 1) wherein the distance between the capacitors (⁋ [0027], “a distance between the trench capacitors 3, may be in a range of 1 micrometer to 3 micrometer”) is smaller than the depth of the capacitors (⁋ [0027], “the depth of the trench capacitor 3 may be in a range of 5 micrometer to 20 micrometer”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize the depth and distances of adjacent trench capacitors as taught by Hosogai with the semiconductor device of Chen ‘903, Choi ‘756, and Choi ‘851 in order to increase the surface area of the capacitor while overall saving space and increasing device density.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm.
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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