Prosecution Insights
Last updated: October 01, 2026
Application No. 18/432,197

INTEGRATED CIRCUIT DEVICE INCLUDING A HIGH THERMAL CONDUCTIVITY ELECTRICALLY INSULATING STRUCTURE

Non-Final OA §103
Filed
Feb 05, 2024
Priority
Oct 12, 2023 — provisional 63/589,689
Examiner
CHOUDHRY, MOHAMMAD M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
589 granted / 718 resolved
+14.0% vs TC avg
Moderate +12% lift
Without
With
+12.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
25 currently pending
Career history
740
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
76.0%
+36.0% vs TC avg
§102
10.8%
-29.2% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 718 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-11 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ohmi (EP 2059103, hereinafter Ohmi). With respect to claim 1, Ohmi discloses an integrated circuit (IC) device (Fig. 1), comprising: a substrate (100); a plurality of electrically conductive structures disposed over the substrate and separated from each other (Para 0014 -0015 – multilayer wiring structure formed on the substrate separated by insulating material); and at least one electrically insulating structure disposed over the substrate and directly contacting each of the plurality of electrically conductive structures (Para 0048 – interlayer insulating layer with a dummy hole). In the same embodiment, Ohmi does not explicitly disclose that the at least one electrically insulating structure having a thermal conductivity greater than five watts per meter-Kelvin (W/m-K). In another embodiment, Ohmi discloses that the at least one electrically insulating structure having a thermal conductivity greater than five watts per meter-Kelvin (W/m-K) (Para 0050-0051 – dummy hole is filled with SiCN which has a thermal conductivity as high as approximately 100W /mK).Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ohmi’s first embodiment by having disclosure from the second embodiment in order to protect the device from overheating. With respect to claim 3, Ohmi discloses wherein the at least one electrically insulating structure comprises at least one of diamond, aluminum nitride (AIN), silicon carbide (SiC), silicon nitride (SiN), boron nitride (BN), or beryllium oxide (BcO) (Para 0030 & 0051 – AlN, SiN & SiCN). With respect to claim 4, Ohmi discloses wherein the at least one electrically insulating structure contacts a lower surface of each of the plurality of electrically conductive structures (Para 0016). With respect to claim 5, Ohmi discloses wherein the at least one electrically insulating structure contacts a surface of each of the plurality of electrically conductive structures that faces the substrate (Para 0016 – insulating layer between wiring layers – the insulating layer contacts the lower surface of the upper wiring layer and the upper surface of the lower wiring layer- wherein the lower surface of the wiring layer faces the substrate). With respect to claim 6, Ohmi discloses wherein the at least one electrically insulating structure contacts a surface of each of the plurality of electrically conductive structures that faces away from the substrate (Para 0016 – insulating layer between wiring layers – the insulating layer contacts the lower surface of the upper wiring layer and the upper surface of the lower wiring layer- wherein the upper surface of the wiring layer faces away from the substrate). With respect to claim 7, Ohmi discloses wherein the at least one electrically insulating structure contacts a face of each of the plurality of electrically conductive structures that faces a neighboring one of the plurality of electrically conductive structures (Para 0014; 0017 and 0019). With respect to claim 8, Ohmi discloses wherein the at least one electrically insulating structure is a single contiguous electrically insulating layer (Para 0021; 0066 and 405 of Fig. 4A). With respect to claim 9, Ohmi discloses wherein the at least one electrically insulating structure comprises a plurality of electrically insulating structures, each of the plurality of electrically insulating structures having a lateral longitudinal axis extending perpendicular to a lateral longitudinal axis of each of the plurality of electrically conductive structures (Para 0057; 0060-0061– 316 of Fig. 3). With respect to claim 10, Ohmi discloses wherein the at least one electrically insulating structure comprises a plurality of electrically insulating structures, each of the plurality of electrically insulating structures filling a majority of a space between each of the plurality of electrically conductive Structures (Para 0057; 0060-0061 and 316 of Fig. 3). With respect to claim 11, Ohmi discloses at least one first additional electrically conductive structure disposed between the substrate and the plurality of electrically conductive structures (Fig. 3); and at least one first electrically conductive via coupling one of the at least one first additional electrically conductive structure to one of the plurality of electrically conductive structures (Para 0048 – via hole). With respect to claim 13, Ohmi discloses an integrated circuit (IC) device (Fig. 1), comprising: a substrate (100); a first dielectric layer disposed over the substrate (Para 0019 – gas or an insulating material); a plurality of electrically conductive structures disposed over the first dielectric layer and separated from each other (Para 0014 -0015 – multilayer wiring structure formed on the substrate separated by insulating material); and at least one electrically insulating structure disposed over the first dielectric layer and adjoining each of the plurality of electrically conductive structures (Para 0048 – a dummy hole). In the same embodiment, Ohmi does not explicitly disclose that the at least one electrically insulating structure having a thermal conductivity greater than a thermal conductivity of the first dielectric layer. In another embodiment, Ohmi discloses that the at least one electrically insulating structure having a thermal conductivity greater than a thermal conductivity of the first dielectric layer (Para 0006; 0015; and 0050-0051). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ohmi’s first embodiment by having disclosure from the second embodiment in order to protect the device from overheating. With respect to claim 14, Ohmi discloses wherein the at least one electrically insulating structure comprises an additional electrically insulating layer contacting the first dielectric layer (Para Fig. 1- Para 0027 – there are multiple insulation films). With respect to claim 15, Ohmi discloses a first additional dielectric layer disposed over and contacting the first dielectric layer (Fig. 1- Para 0027 – there are multiple insulation films), wherein the at least one electrically insulating structure is disposed over and contacts the first additional dielectric layer (Para 0050-0051) and the thermal conductivity of the at least one electrically insulating structure is greater than a thermal conductivity of the first additional dielectric layer (Para 0006; 0015; and 0050-0051). With respect to claim 16, Ohmi discloses a first electrically conductive structure disposed in the first dielectric layer (Para 0014; 0017 and 0019); a first electrically conductive via connecting the first electrically conductive structure to at least one of the plurality of electrically conductive structures (Para 0048 – via hole); and a second dielectric layer disposed over the at least one electrically insulating structure and the plurality of electrically conductive structures (Fig. 1 – there are multiple insulating layers); a second electrically conductive structure disposed in the second dielectric layer (Para 0014; 0017 and 0019); and a second electrically conductive via connecting the second electrically conductive structure to one of the at least one of the pluralities of electrically conductive structures (Para 0048 – via hole). With respect to claim 17, Ohmi discloses a method, comprising: providing a substrate (100); forming a first dielectric layer over the substrate (Para 0019 – gas or an insulating material); and forming a plurality of electrically conductive structures and at least one electrically insulating structure over the first dielectric layer (Para 0014 -0015 – multilayer wiring structure formed on the substrate separated by insulating material), the at least one electrically insulating structure adjoining each of the plurality of electrically conductive structures (Para 0048 – a dummy hole). In the same embodiment, Ohmi does not explicitly disclose that the at least one electrically insulating structure having a thermal conductivity greater than a thermal conductivity of the first dielectric layer. In another embodiment, Ohmi discloses that the at least one electrically insulating structure having a thermal conductivity greater than a thermal conductivity of the first dielectric layer (Para 0006; 0015; and 0050-0051). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ohmi’s first embodiment by having disclosure from the second embodiment in order to protect the device from overheating. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ohmi in view of Sethi et al. (US 5573973, hereinafter Sethi). With respect to claim 2, Ohmi does not explicitly disclose wherein the at least one electrically insulating structure comprises diamond. In an analogous art, Sethi discloses wherein the at least one electrically insulating structure comprises diamond (Col. 8; lines 54-65 – insulating diamond film). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ohmi’s device by having Sethi’s disclosure in order to improve the insulation properties of a semiconductor device. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ohmi in view of Wei et al. (US 2022/0293517, hereinafter Wei). With respect to claim 12, Ohmi discloses at least one second additional electrically conductive structure disposed over the plurality of electrically conductive structures opposite the substrate (Para 0014 -0015 – multilayer wiring structure formed in a stack). Ohmi does not explicitly disclose at least one second electrically conductive via coupling one of the at least one second additional electrically conductive structure to one of the plurality of electrically conductive structures. In an analogous art, Wei discloses at least one second electrically conductive via coupling one of the at least one second additional electrically conductive structure to one of the plurality of electrically conductive structures (Para 0013 -0013 – one or more stacked vias). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ohmi’s device by having Wei’s disclosure in order to connect different components of a semiconductor device. Claim 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ohmi in view of Gaul et al. (US 2011/0140232, hereinafter Gaul) and further in view of Leedy (US 2016/0155722, hereinafter Leedy). With respect to claim 18, Ohmi discloses the method of claim 17. Ohmi discloses wherein the at least one electrically insulating structure comprises a plurality of electrically insulating structures (Para 0016-0017), and wherein the method further comprises: Ohmi does not explicitly disclose forming a second dielectric layer over the first dielectric layer prior to forming the plurality of electrically conductive structures and the plurality of electrically insulating structures, wherein forming the plurality of electrically insulating structures comprises: etching a plurality of trenches in the second dielectric layer through an upper surface of the second dielectric layer; seeding the plurality of trenches and the upper surface of the second dielectric layer with crystals of an electrically insulating material having a thermal conductivity greater than a thermal conductivity of the second dielectric layer; growing grains of the electrically insulating material on the crystals of the electrically insulating material; and removing the grains and the crystals not disposed in the plurality of trenches from the second dielectric layer. In an analogous art, Gaul discloses forming a second dielectric layer over the first dielectric layer prior to forming the plurality of electrically conductive structures (Para 0032 – silicon oxide) and the plurality of electrically insulating structures (Fig. 3), wherein forming the plurality of electrically insulating structures comprises: etching a plurality of trenches in the second dielectric layer through an upper surface of the second dielectric layer (Para 0032; and Fig. 4-5); seeding the plurality of trenches and the upper surface of the second dielectric layer with crystals of an electrically insulating material (Para 0035 -0036; 0041– seed layer of diamond); growing grains of the electrically insulating material on the crystals of the electrically insulating material (Para 0035-0036; 0041; 0060); and removing the grains and the crystals not disposed in the plurality of trenches from the second dielectric layer (Para 0036; and 0044). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ohmi’s device by having Gaul’s disclosure in order to isolate different components to avoid short circuiting. Ohmi/Gaul does not explicitly disclose that the electrically insulating material having a thermal conductivity greater than a thermal conductivity of the second dielectric layer. In an analogous art, Leedy discloses that the electrically insulating material having a thermal conductivity greater than a thermal conductivity of the second dielectric layer (Para 0633). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ohmi’s device by having Sethi’s disclosure in order to improve the insulation properties of a semiconductor device. With respect to claim 19, Ohmi/Gaul/Leedy discloses the method of claim 17. Ohmi does not explicitly disclose wherein the grains and the crystals not disposed in the plurality of trenches are removed using chemical-mechanical planarization. In an analogous art, Leedy discloses wherein the grains and the crystals not disposed in the plurality of trenches are removed using chemical-mechanical planarization (Para 0036 and 0039). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ohmi’s device by having Gaul’s disclosure in order to clean and smooth the surfaces. With respect to claim 20, Ohmi/Gaul/Leedy discloses the method of claim 18. Ohmi does not explicitly disclose wherein the electrically insulating material comprises diamond. In an analogous art, Leedy discloses wherein the electrically insulating material comprises diamond (Para 0030 and 0036). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ohmi’s device by having Gaul’s disclosure in order to improve the insulation of a semiconductor device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Feb 05, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751255
IC CHIP MOUNTING DEVICE AND IC CHIP MOUNTING METHOD
3y 7m to grant Granted Sep 29, 2026
Patent 12740186
LIGHT EMITTING DIODES WITH ALUMINUM-CONTAINING LAYERS INTEGRATED THEREIN AND ASSOCIATED METHODS
5y 4m to grant Granted Sep 15, 2026
Patent 12740196
MICRO LIGHT-EMITTING ELEMENT AND MICRO LIGHT-EMITTING ELEMENT DISPLAY DEVICE
3y 10m to grant Granted Sep 15, 2026
Patent 12740352
SUBSTRATE PROCESSING METHOD
3y 1m to grant Granted Sep 15, 2026
Patent 12727418
PLASMA DICED WAFERS AND METHODS THEREOF
3y 9m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+12.0%)
2y 9m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 718 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month