Prosecution Insights
Last updated: October 02, 2026
Application No. 18/432,328

DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE

Non-Final OA §102§103
Filed
Feb 05, 2024
Priority
Jul 06, 2023 — RE 10-2023-0087839
Examiner
WARD, ERIC A
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
589 granted / 754 resolved
+10.1% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
25 currently pending
Career history
774
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
58.4%
+18.4% vs TC avg
§102
21.0%
-19.0% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 754 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/20/2026. Claim Objections Claim 3 objected to because of the following informalities: Claim 3 line 1 “wherein a width the first partition” should be “wherein a width of the first partition”. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 9 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2019/0115560 A1 to KIM, “Kim `560”. Regarding claim 1, Kim `560 discloses a display device (e.g. FIG. 2 or FIG. 11) comprising: a pixel circuit layer (substrate 100 includes TFTs Tr e.g. FIG. 11); a partition wall (201a, ¶ [0063]) above the pixel circuit layer; a protrusion part (201b, ¶ [0063]) spaced apart from the partition wall in a planar direction, and defining an opening (opening between 201a and 201b); a planarization layer (800, ¶ [0062],[0066],[0067]) in the opening; a first electrode (400, ¶ [0038],[0039]) having at least a portion above the planarization layer; a light-emitting part (600, ¶ [0046]-[0053],[0056]) having at least a portion above the first electrode; and a second electrode (700, ¶ [0059],[0060]) having at least a portion above the light-emitting part. Regarding claim 9, Kim `560 discloses the display device of claim 1, and Kim `560 further discloses wherein the planarization layer (800) fills the opening (as pictured between 201a and 201b), comprises one flat surface (e.g. upper surface), and comprises an organic material (¶ [0066]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-3,5-6,9,12-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0082534 A1 to Kim et al., “Kim `534”, in view of US 2014/0183483 A1 to Kim et al., “Kim `483”. Regarding claim 1, Kim `534 discloses a display device (FIG. 3) comprising: a pixel circuit layer (e.g. TFT layer containing transistor 310, ¶ [0023]); a protrusion part (electrode 363, ¶ [0025],[0026]) defining an opening (filled with 367); a planarization layer (367, ¶ [0028]) in the opening; a first electrode (370, ¶ [0033]-[0035]) having at least a portion above the planarization layer (367); a light-emitting part (380, ¶ [0029]) having at least a portion above the first electrode; and a second electrode (390, ¶ [0031]) having at least a portion above the light-emitting part. Kim `534 fails to clearly teach a partition wall above the pixel circuit layer, the protrusion part spaced apart from the partition wall in a planar direction. Kim `483 teaches (FIG. 1) a partition wall (E3, ¶ [0030]-[0032]) above a pixel circuit layer (e.g. wiring layer containing TFT T and wires W), a protrusion part (E1) spaced apart from the partition wall (E3) in a planar direction. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim `534 with a partition or auxiliary electrode as taught by Kim `483 in order to enhance light emission by improving the connection to the second electrode and enhance display quality (Kim `483 ¶ [0005]-[0010]). Regarding claim 2, Kim `534 in view of Kim `483 yields the display device of claim 1, and Kim `483 further teaches wherein the partition wall (E3) comprises: a first partition wall layer (lower portion formed in FIG. 5) above the pixel circuit layer; and a second partition wall (upper portion(s) formed in FIG. 7 and FIG. 8) layer above the first partition wall layer. Regarding claim 3, Kim `534 in view of Kim `483 yields the display device of claim 2, and Kim `483 further teaches wherein a width (lower portion of E3 in contact with 50) the first partition wall layer (lower portion of E3 formed in FIG. 5) is less than a width of the second partition wall layer (upper portion(s) formed in FIG. 7 and FIG. 8, since E3 tapers outward). Regarding claim 5, Kim `534 in view of Kim `483 yields the display device of claim 2, and Kim `483 further teaches wherein the protrusion part (e.g. height of E1 when applied to Kim `534) has a same height as the first partition wall layer (portion of E3 formed in FIG. 5, since formed from the same process, ¶ [0054]). Regarding claim 6, Kim `534 in view of Kim `483 yields the display device of claim 5, and Kim `483 further teaches wherein the protrusion part (E1 formed in FIG. 5, when applied to Kim `534) and the first partition wall layer (E3 formed in FIG. 5) comprise a same material (since formed from the same process, ¶ [0054]). Regarding claim 9, Kim `534 in view of Kim `483 yields the display device of claim 1, and Kim `534 further teaches wherein the planarization layer (367) fills the opening, comprises one flat surface (e.g. upper surface), and comprises an organic material (formed from layer 366 e.g. resin, ¶ [0027]). Regarding claim 12, Kim `534 discloses a display device (FIG. 3) comprising: a pixel circuit layer (e.g. TFT layer containing transistor 310, ¶ [0023]); a protrusion part (electrode 363, ¶ [0025],[0026]) having a flat surface (e.g. upper surface) spaced from the pixel circuit layer (lower TFT); a first electrode (370, ¶ [0033]-[0035]) having at least a portion above the protrusion part; a light-emitting part (380, ¶ [0029]) having at least a portion above the first electrode; and a second electrode (390, ¶ [0031]) having at least a portion above the light-emitting part. Kim `534 fails to clearly teach a partition wall above the pixel circuit layer, and comprising a first partition wall layer, and a second partition wall layer above the first partition wall layer, the protrusion part spaced apart from the partition wall in a planar direction. Kim `483 teaches (FIG. 1) a partition wall (E3, ¶ [0030]-[0032]) above a pixel circuit layer (e.g. wiring layer containing TFT “T” and wires “W”), comprising a first partition wall layer (lower portion of E3 formed in FIG. 5), and a second partition wall layer (e.g. portions of E3 formed in FIG. 7 and/or FIG. 8) above the first partition wall layer, a protrusion part (E1) spaced apart from the partition wall (E3) in a planar direction. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim `534 with a partition or auxiliary electrode as taught by Kim `483 in order to enhance light emission by improving the connection to the second electrode and enhance display quality (Kim `483 ¶ [0005]-[0010]). Regarding claim 13, Kim `534 in view of Kim `483 yields the display device of claim 12, and Kim `483 further teaches wherein the protrusion part (e.g. E1) and the partition wall (E3) are at a same plane. Regarding claim 14, Kim `534 in view of Kim `483 yields the display device of claim 13, and Kim `534 further teaches wherein the first partition wall layer and the protrusion part comprise aluminum (AI) (e.g. may be formed of Al/ITO ¶ [0029]), and Kim `534 further teaches wherein the first electrode (370) entirely overlaps with the protrusion part in a plan view (“370 is formed on the entire surface of the first pixel electrode 363” ¶ [0033]). Claims 2,7,8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0115560 A1 to KIM, “Kim `560”, in view of US 2016/0351638 A1 to IM et al., “Im”. Regarding claim 2, although Kim `560 discloses the display device of claim 1, Kim `560 fails to clearly teach wherein the partition wall (201a) comprises: a first partition wall layer above the pixel circuit layer and a second partition wall layer above the first partition wall layer. Im teaches wherein a partition wall (e.g. 190 or 180 when applied to Kim `560) comprises a first partition wall layer (e.g. 191 or 181, ¶ [0057],[0060]) above a pixel circuit layer (e.g. TFT T), and a second partition wall layer (e.g. 192 or 182, ¶ [0057],[0060]) above the first partition wall layer. More generally, Im teaches wherein the conductive features (180 and 190) comprise multiple layers. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim `560 with at least two layers as taught by Im in order to add superior corrosion resistance (Im ¶ [0057],[0060]). Regarding claim 7, Kim `560 in view of Im yields the display device of claim 2, and Kim `560 as modified by Im further yields wherein the protrusion part (Kim `560 portion 201b) comprises: a first protrusion part (Im layer 181 or 192 when applied to Kim `560) above the pixel circuit layer; and a second protrusion part (Im layer 182 or 192 when applied to Kim `560) above the first protrusion part, wherein the first protrusion part (layer 181) has a same height as the first partition wall layer (since formed from the same material in the same process step), and wherein the second protrusion part (layer 182/192) has a same height as the second partition wall layer (since formed from the same material in the same process step). Regarding claim 8, Kim `560 in view of Im yields the display device of claim 7, and Kim `560 as modified by Im further yields wherein the first protrusion part and the first partition wall layer (Im layer 181/191) comprise a same material (since formed from the same material in the same process step), and wherein the second protrusion part and the second partition wall layer (Im 182/192)comprise a same material (since formed from the same material in the same process step). Claims 1,2,4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0082534 A1 to Kim et al., “Kim `534”, in view of in view of US 2021/0376283 A1 to SHIN et al., “Shin”. Regarding claim 1, Kim `534 discloses a display device (FIG. 3) comprising: a pixel circuit layer (e.g. TFT layer containing transistor 310, ¶ [0023]); a protrusion part (electrode 363, ¶ [0025],[0026]) defining an opening (filled with 367); a planarization layer (367, ¶ [0028]) in the opening; a first electrode (370, ¶ [0033]-[0035]) having at least a portion above the planarization layer (367); a light-emitting part (380, ¶ [0029]) having at least a portion above the first electrode; and a second electrode (390, ¶ [0031]) having at least a portion above the light-emitting part. Kim `534 fails to clearly teach a partition wall above the pixel circuit layer, the protrusion part spaced apart from the partition wall in a planar direction. Shin teaches (e.g. FIG. 4) a partition wall (130, ¶ [0057],[0058]) above a pixel circuit layer (e.g. above TFT T1), the protrusion part (electrode 151, protrusion when applied to Kim `534) is spaced apart from the partition wall (130) in a planar direction. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim `534 with a partition wall (i.e. auxiliary electrode) as taught by Shin in order to benefit from Shin’s decreased or minimized leakage current (Shin ¶ [0006],[0008],[0010],[0016]) and prevent cathode voltage decrease which can cause luminance unevenness (Shin ¶ [0007]). Regarding claim 2, Kim `534 in view of Shin yields the display device of claim 1, and Shin further discloses wherein a partition wall (130) comprises a first partition wall (e.g. 132, ¶ [0073]-[0075]) above a pixel circuit layer (e.g. above T1), and a second partition wall layer (133) above the first partition wall (132). Regarding claim 4, Kim `534 in view of Shin yields the display device of claim 2, and Shin further discloses wherein the first partition wall layer (132) comprises aluminum (Al) (¶ [0074]), and wherein the second partition wall layer (133) comprises titanium (Ti) (¶ [0074]). Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2005/0082534 A1 to Kim et al., “Kim `534”, in view of US 2014/0183483 A1 to Kim et al., “Kim `483”, as applied to claim 9 above, further in view of US 2018/0323404 A1 to INOUE et al., “Inoue”. Regarding claim 10, although Kim `534 in view of Kim `483 yields the display device of claim 9, wherein a difference between a thickness of the planarization layer and a thickness of the protrusion part is about 0 Å to about 1000 Å. Kim `534 teaches wherein the difference in thickness between the planarization layer (367) and a thickness of the protrusion (363) is equal to the thickness of the protrusion electrode (368). Inoue teaches wherein a protrusion electrode (3) has a thickness of 1000 Å (100 nm ¶ [0074]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Kim `534 in view of Kim `483 with the thickness of the electrode (and therefore thickness difference between the planarization layer and a thickness of the protrusion) as taught by Inoue since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the thickness of the electrode determines the electrical properties of the light emitter such as current capability of the electrode or physical properties such as the thickness of the resulting light emitter stack making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized. Regarding claim 11, Kim `534 in view of Kim `483 and Inoue yields the display device of claim 10, and Kim `534 further teaches wherein the first electrode (370) and the protrusion part (363) are electrically connected to each other (as pictured). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2015/0221893 A1 to Teraguchi et al. teaches a planarization layer (15) which forms a raised region below a first electrode (21) for controlling light emission (FIG. 13). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Eric A. Ward/Primary Examiner, Art Unit 2891
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Prosecution Timeline

Feb 05, 2024
Application Filed
Sep 04, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
91%
With Interview (+13.3%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 754 resolved cases by this examiner. Grant probability derived from career allowance rate.

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