DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 7 is objected to because of the following informalities: Claim 7 has quotes it appears these should be underline. Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the Claims 21-23 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
If the conductive feature is indeed “source/drain” applicant must show the rest of the transistor including how the gate relates to these source/drain.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As to claims 21-23 Applicant does not have support for source drains on the substrate. Claims 1 and 7 state a first conductive feature disposed on the substrate; a second conductive feature disposed on the substrate.
The specification states with respect to the source drain:
In some embodiments, the substrate 101 also includes various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, lightly doped region (LDD), heavily doped source and drain (S/D), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a complimentary metal-oxide-semiconductor field-effect transistor (CMOSFET), imaging sensor, and/or light emitting diode (LED).
The doped regions are therefore in the substrate not on as claimed.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1,3,5-7, 9-10 12-13 ,and 21-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
a. As to claims 1 and 7, recitation of to form is an intended outcome and does not require the element this creates antecedent basis issues with the term resistor since there was no first and second resistor positively claimed.
So, the conductive feature would not be on the substrate but instead be in the substrate.
Claims 12 and 13 are unclear how the capacitor relates to the method of claim 12-13
Claims 14-15 clarifies the capacitor structure relationship and overcomes the 112b.
As to claim 21-23 the claims are inconsistent with the normal interpretation of source drain.
b. Claims 1 and 7 recites a first conductive feature disposed on the substrate however source drains are forming as doping region in the substrate. Thus, a source drain would necessarily be in the substrate not on the substrate.
Specifically, paragraph 22 of applicant states : In some embodiments, the substrate 101 also includes various p-type doped regions and/or n-type doped regions, implemented by a process such as ion implantation and/or diffusion. Those doped regions include n-well, p-well, lightly doped region (LDD), heavily doped source and drain (S/D), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as a complimentary metal-oxide-semiconductor field-effect transistor (CMOSFET), imaging sensor, and/or light emitting diode (LED).
It appears claims 21-23 are a different embodiment then the source drain since if the conductive features are on the substrate that would indicate they are mentalizations and not doped regions.
c. As to claim 21-23 it is unclear of the scope source/drain implies a transistor however applicant is not claiming a gate. Further the scope is unclear since is applicant referring only a doped regions or can a source drain include a contact. The office will interpret source/drain to include the metal contact thus the metal contact can be on the substrate and not be in the substrate as precluded by claims 1 and 7.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Loke previously cited.
a. As to claim 1, Loke teaches A semiconductor device, comprising: a substrate; a first conductive feature disposed on the substrate (figure 16 items 104 0r 106)item 121b or a figure 1C); a second conductive feature disposed on the substrate (the other of 104 or 106); a first via structure formed on the first conductive feature (152 or 154); a second via structure formed on the second conductive feature (the other of 152 or 54); and a metal-insulator-metal (MIM) structure disposed on the substrate, wherein the MIM structure comprises a first metallization layer (item 114), a first insulating layer (item 116) and a second metallization layer (item 120), the first insulating layer is located between the first and second metallization layers (item 116 between the two), wherein the first metallization layer is electrically connected to the first and second via structures to form a first resistor between the first and second via structures (114 is directly connected to item 152 electrically connected to 120 which electrically connected to 154 thus 114 is electrically connected to 152 and 154 114 is not a super conductor thus it has some sort of resistance), and the second metallization layer is electrically connected to the first and second via structures ( item 120 is directly connect to 152 electrically connected to item 114 which in turns is electrically connect to item 152 thus 120 is electrically connected to 152 and 154 and is not a superconductor at superconductor temperature thus acting as a second resistor) to form a second resistor between the first and second via structures, wherein the MIM structure further comprises a third metallization layer (item 126), a second insulating layer (item 122) and a fourth metallization layer (item 132), the second insulating layer is located between the third and fourth metallization layers (126 and 132 form a capacitor as well as two resistors), and a capacitor is formed between the third metallization layer and the fourth metallization layer, wherein the capacitor , the first resistor and the second resistor are connected in parallel and stacked vertically to each other (they are in a parallel connection). The claim does not require that they are in parallel with respect to each other only connected in parallel which they are connected parallel since the capacitor is connect in parallel with respect to the two resistors.
Claim(s) 1,3,6,7,and 9-23 is is/are rejected under 35 U.S.C. 102a1 as being anticipated by Wu previously cited.
a. As to claim 1, Wu teaches A semiconductor device, comprising: a substrate (figure 1D item 122); a first conductive feature disposed on the substrate (item 112a on the side of 122); a second conductive feature disposed on the substrate (item 112b); a first via structure formed on the first conductive feature (item 90a); a second via structure formed on the second conductive feature (item 90 b); and a metal-insulator-metal (MIM) structure disposed on the substrate (items 41-49 paragraph 13), wherein the MIM structure comprises a first metallization layer (item 41), a first insulating layer (item 10 between item 43 and 45) and a second metallization layer (item 45a), the first insulating layer is located between the first and second metallization layers (item 10 between 41 and 45), wherein the first metallization layer is electrically connected to the first and second via structures to form a first resistor between the first and second via structures (it is electrically connected to 43 and 41 and 43 are non-superconductor thus resistive), and the second metallization layer is electrically connected to the first and second via structures to form a second resistor between the first and second via structures (item 45a is directly connected to 90a is electrically connected to 45b which connects to 45b both are resistive since they are not superconductor), wherein the MIM structure further comprises a third metallization layer (item 45c), a second insulating layer (item 10 on 45) and a fourth metallization layer (item 49), the second insulating layer is located between the third and fourth metallization layers (item 10 between item 45c and 49), and a capacitor is formed between the third metallization layer and the fourth metallization layer (45c and 49 are a capacitor), wherein the capacitor, the first resistor and the second resistor are connected in parallel and stacked vertically to each other (the defined resistors and capacitors are in parallel with respect to each other.
b. As to claim 3, Wu teaches wherein the third metallization layer is electrically connected to the first via structure but is from separated from the second via structure (by definition the 45 that is directly connect to the first via is third but not directly to the second), and the fourth metallization layer is electrically connected to the second via structure but is from separated from the first via structure (the on above is directly connected to the second via but not directly connected to the first).
c. As to claim 7, Wu teaches A semiconductor device, comprising: a substrate (figure 1D item 122); a first conductive feature disposed on the substrate (item 121a); a second conductive feature disposed on the substrate (item 121b); a first via structure formed on the first conductive feature (90a); a second via structure formed on the second conductive feature (90b); and a metal-insulator-metal (MIM) structure disposed on the substrate (41-49 paragraph 13), wherein the MIM structure comprises a first metallization layer (item 41), a first insulating layer (item 10), a second metallization layer (item 45b), a second insulating layer (item 10) and a third metallization layer (item 45c), the first insulating layer is located between the first and second metallization layers (item 10), the second insulating layer is located between the second and third metallization layers (item 10) ,wherein the first metallization layer is electrically connected to the first and second via structures to form a resistor (it is electrically connected through 43 it is not a superconductor thus has some resistance), the second metallization layer is electrically connected to the second via structure (45b) but is from separated from the first via structure (not directly connect to 90a), and the third metallization layer is electrically connected to the first via structure (item 45c) but is from separated from the second via structure (it is not directly connected to 90b), and a first capacitor is formed between the second metallization layer and the third metallization layer (by definition) ,wherein the resistor is connected in parallel with the first capacitor and vertically stacked to each other (they are stacked and it parallel with one another).
d. As to claim 9, Wu teaches wherein the MIM structure further comprises a third insulating layer and a fourth metallization layer (item 10 and 49 respectively), the third insulating layer is located on the third metallization layer and the fourth metallization layer (item 10 is on 45c), wherein the fourth metallization layer is electrically connected to the second via structure (it is directly connect to item 90b) but is separated from the first via structure it is not directly connected to 90a), and a second capacitor is formed between the third metallization layer and the fourth metallization layer (by definition).
e. As to claim 10, Wu teaches resistor, the first capacitor and the second capacitor are connected in parallel and vertically stacked to each other (due to how they are connected to the vias they are in parallel.
f. As to claim 11, Wu teaches A method of manufacturing a semiconductor device, including (figures 5): forming a metal-insulator-metal (MIM) structure on a substrate (items 41-49 figure 1d on item 122), the MIN structure comprises a plurality of metallization layers stacked vertically to each other (paragraph 13); forming a first via structure on a first conductive feature (90a on 121a figure 5f to 5g)), the first via structure penetrating the MIM structure (see figure 1D figure), the first via structure being electrically connected to at least one of the metallization layers (figure 1D); forming a second via structure on a second conductive feature (item 90b on 121b), the second via structure penetrating the MIM structure, the second via structure being electrically connected to at least one of the metallization layers (items 41-49 are electrically connected to the vias) or at least one resistor and at least one capacitor are electrically connected between the first and second via structures and stacked vertically to each other through the MIM structure (Each capacitor is in parallel and made up of a resistive material sic not a superconductor thus the structure has capacitor and resistors).
g. As to claims 12-15, Wu teaches wherein forming the MIM structure comprises: providing a substrate (figure 1D item 122); and forming each of:
a first conductive feature disposed on the substrate (item 121a); a second conductive feature disposed on the substrate (item 121b); a first via structure formed on the first conductive feature (90a); a second via structure formed on the second conductive feature (90b); and a metal-insulator-metal (MIM) structure disposed on the substrate (41-49 paragraph 13), wherein the MIM structure comprises a first metallization layer (item 41), a first insulating layer (item 10), a second metallization layer (item 45b), a second insulating layer (item 10) and a third metallization layer (item 45c), the first insulating layer is located between the first and second metallization layers (item 10), the second insulating layer is located between the second and third metallization layers (item 10) ,wherein the first metallization layer is electrically connected to the first and second via structures to form a resistor (it is electrically connected through 43 it is not a superconductor thus has some resistance), the second metallization layer is electrically connected to the second via structure (45b) but is from separated from the first via structure (not directly connect to 90a), and the third metallization layer is electrically connected to the first via structure (item 45c) but is from separated from the second via structure (it is not directly connected to 90b), and a first capacitor is formed between the second metallization layer and the third metallization layer (by definition) ,wherein the resistor is connected in parallel with the first capacitor and vertically stacked to each other (they are stacked and it parallel with one another).
h. As to claim 16-19, Wu teaches providing a substrate (figure 1D item 122);
forming each of: a first conductive feature disposed on the substrate (item 121a); a second conductive feature disposed on the substrate (item 121b); a first via structure formed on the first conductive feature (90a figure this is formed after the MIM figures 5e-5g); a second via structure formed on the second conductive feature (90b formed after the MIM figure 5e-5g); and a metal-insulator-metal (MIM) structure disposed on the substrate (41-49 paragraph 13), wherein the MIM structure comprises a first metallization layer (item 41), a first insulating layer (item 10), a second metallization layer (item 45b), a second insulating layer (item 10) and a third metallization layer (item 45c), the first insulating layer is located between the first and second metallization layers (item 10), the second insulating layer is located between the second and third metallization layers (item 10) ,wherein the first metallization layer is electrically connected to the first and second via structures to form a resistor (it is electrically connected through 43 it is not a superconductor thus has some resistance), the second metallization layer is electrically connected to the second via structure (45b) but is from separated from the first via structure (not directly connect to 90a), and the third metallization layer is electrically connected to the first via structure (item 45c) but is from separated from the second via structure (it is not directly connected to 90b), and a first capacitor is formed between the second metallization layer and the third metallization layer (by definition) ,wherein the resistor is connected in parallel with the first capacitor and vertically stacked to each other (they are stacked and it parallel with one another).
h. As to claim 6 and 20, Wu does not explicitly teach the MIM structure has a thickness of 200-1000 nanometers.
Wu teaches 40 nm for the conductor and 6 nm for the insulator. Since there are 8 terminal that is 320 nm and 5 insulators for 30 nm providing an overall thickness of 350nm thus while not explicitly presented it is implicitly provided.
i. As to claims 21-23, In view of the 112b the elements 121a and 12b could be contacts for a transistor source/drain, applicant is not element by providing the label thus Wu teaches:
Claim 21, wherein the first conductive feature is a source/drain region, and the first via structure is configured to penetrate the MIM structure and electrically connected to the first conductive feature.
Claim 22, wherein the second conductive feature is a source/drain region, and the second via structure is configured to penetrate the MIM structure and electrically connected to the second conductive feature.
Claim 23 wherein the first conductive feature and the second feature are source/drain regions, the first via structure is configured to penetrate the MIM structure and electrically connected to the first conductive feature, and the second via structure is configured to penetrate the MIM structure and electrically connected to the second conductive feature.
Claim Rejections - 35 USC § 103
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Ding 20200235087 and Yi 20180226453 and Chen previously cited
a. As to claim 5, Wu does not teach wherein each of the first resistor and the second resistor has a resistance of 1-20 ohms. Yi teaches integrating resistors in the same mentalizations of the MIM capacitor structures (figure 3 item RL1 RL2 integrated with C1 and C2 respectively). Ding teaches forming a resistor is insulators below the capacitors figure 2 item 630 under 500 also figure 9 wherein the resistor is connected to at least one common via and figure 10 as well. Chen teaches it was known to provide resistors an capacitor in parallel figure 6a. Further capacitor in parallel are known to provide CTotal= C1+C2+C3…+Cn where the C1-Cn are the capacitor in parallel Ctotal is effective capacitance.
Where for resistor 1/Rtotal=1/R1+1/R2+1/R3…+1/Rn where R1-Rn are the resistors in parallel and Rtotal is the effective total resistance.
Further resistor in semiconductor device were known to have 1 to 20 ohms
Thus, it would have been obvious to one of ordinary skill in the art to provide integrate as the first two mentalizations of the MIM structure of two resistors each having the same resistance of 1 to 20 ohms to provide an effective resistance of between ½ ohm and 10 ohms. Allowing resistors to be formed with conventional material used in semiconductor fabrication but providing a lower overall resistance then would be capable of by themselves Allow for the resistor Capacitor circuit parallel structure to be formed in a single MIM structure.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 7 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/ Primary Examiner, Art Unit 2896
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