DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election without traverse of Species I-1 (shown in Figs. 1A-1J) of Invention I (directed to a method) in the Response to Restriction Requirements (filed 06/08/26) has been acknowledged.
Together with the Response, Applicant amended a few paragraphs of the specification, submitted two sheets with replacement figures and cancelled device Claims 16-20.
Applicant also added new method Claims 21-25 and stated that Claims 1-15 and 21-25 are read on the elected species. However,
Claim 5, citing a photonic substrate comprising an etch stop layer – does not belong to Species I-1 – it belongs to Species I-2 (Species I-1 has an etch stop layer 125 in the electrical substrate 120).
Claim 9, claiming a ratio of a distance and a length, is also directed to Species I-2; this is supported by paragraph 0084 of the published application US 2025/0253292 that describes an embodiment of Figs. 2A-2D.
Claims 4 and 13, recite a limitation: “the (first) conductive via structure extends into the first wiring layer”- that is not shown in Figs. 1A-1J, but is shown in Fig. 6 (see paragraph 0095 of the published application);
Claim 15, citing that the conductive via structure is in direct contact with the second dielectric structure – is described for a structure of Fig. 3 (in paragraph 0089 of the published application; note that the second dielectric structure belongs to the electrical substrate, in accordance with Claim 14) – this limitation is not read on a method of Figs. 1A-1J.
Status of Claims
Claims 4, 5, 9, 13, and 15 are withdrawn from further consideration as being drawn to nonelected inventions.
Claims 1-3, 6-8, 10-12, 14, and 21-25 are examined on merits herein.
However, as it is common in the USPTO examination procedure, when a chosen species is allowed, non-chosen species comprising all limitations of an allowable basic claim would be considered for rejoinder.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s):
“the photonic substrate further comprises a second wiring layer in the dielectric structure and connected between the first wiring layer and the second conductive via structure”, as Claim 3 recites, where the first wiring layer is connected to the first conductive via structure, per Claim 1, e.g., - the second wiring layer with its connections shall be shown.
“the first conductive via structure is in direct contact with the first wiring layer”, wherein “the first wiring layer is in direct contact with the second bonding dielectric layer”, as Claim 1 recites – current figures of the application show that a wiring layer contacting a second bonding structure is different from a wiring layer being in direct contact with a first conductive via.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 1 recites: “the first conductive via structure is in direct contact with the first wiring layer” and “the first wiring layer is in direct contact with the second bonding dielectric layer”; however, the specification does not support the combination of recitations, and teaches that different wiring layers contact the second bonding wiring layer 116 and the first conductive via structure 136b: See Annotated Fig. 1H of the current application for convenience:
Annotated Fig. 1H
PNG
media_image1.png
424
516
media_image1.png
Greyscale
Claim 3 recites: “the photonic substrate further comprises a second wiring layer in the dielectric structure and connected between the first wiring layer and the second conductive via structure”, but the specification does not teach a second wiring layer connected between the first wiring layer and the second conductive via structure.
Claim Objections
Claim 21 is objected to because of the following informalities:
Claim 21 recites (lines 4-6): “the electrical substrate comprises a substrate, a wiring layer, an etch stop layer, a first dielectric structure, and a first bonding pad, the wiring layer, the etch stop layer, the first dielectric structure” Examiner suggests using a semi-column between different statements, e.g.: “the electrical substrate comprises a substrate, a wiring layer, an etch stop layer, a first dielectric structure; and a first bonding pad; the wiring layer, the etch stop layer, the first dielectric structure”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3, 6-8, 10, and 21-25 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 1: Claim 1 recites: “the first conductive via structure is in direct contact with the first wiring layer” and “the first wiring layer is in direct contact with the second bonding dielectric layer”. The combination of the recitation is unclear, since conflicts with the specification of the application, as is shown in objections to the specification.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, Claim 1 was interpreted such that the second of the above-cited recitation was omitted from consideration.
In re Claim 3: Claim 3 recites: “the photonic substate further comprises a second wiring layer in the dielectric structure and connected between the first wiring layer and the second conductive via structure”. However, it is not clear what a second wiring layer is, considering that Claim 3 depends on Claim 1, and Claim 1 recites: “the second conductive via structure is spaced apart from the first wiring layer” and also recites that “the first conductive via structure is in direct contact with the first wiring layer”. For a better clarity or arguments, Annotated Fig. 1H is shown below
Based on this figure and in view of identifications of the first and second vias by Claim 1, it is clear that the second conductive via is via 136a (since it is separated from any wiring identified by number 115), while the first conductive via structure is 136b. As Fig. 1H shows, there are no wiring layer connected between the first wiring layer 115M and second conductive via structure 136a.
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation of Claim 3 was interpreted as: “the photonic substate further comprises a second wiring layer in the dielectric structure”, e.g., a portion of the limitation related to connection of the second wiring layer was omitted from consideration.
In re Claim 7: Claim 7 recites: “the first conductive via structure is longer than the second conductive via structure”. Claim 7 depends on Claim 1, where Claim 1 recites: “first conductive via structure is in direct contact with the first wiring structure”, meaning that the first conductive via structure is 136b, which is shorter than 136a (see Annotated Fig. 1H), which makes the recitation of Claim 7 unclear, as contradicting Fig. 1H and its description in the specification.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, however, Claim 7 was interpreted as filed.
In re Claims 2, 6, 8, and 10: Claims 2, 6, 8, and 10 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
In re Claim 21: Lines 4-6 of Claim 21 recite: “the electrical substrate comprises a substrate, a wiring layer, an etch stop layer, a first dielectric structure, and a first bonding pad; the wiring layer, the etch stop layer, the first dielectric structure, and the first bonding pad are sequentially stacked over the substrate”. The recitation is unclear, since the first dielectric structure disposed over the etch stop layer 125 (see Annotated Fig. 1H) shall be layer 126, but the first bonding pad 127 is described by the specification as being disposed in layer 126 (see paragraph 0045 of the published application), not on the layer 126.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required.
For this Office Action, the cited limitation was interpreted in line with the specification as: “the electrical substrate comprises a substrate, a wiring layer, an etch stop layer, a first dielectric structure, and a first bonding pad; the wiring layer, the etch stop layer, and the first bonding pad in the first dielectric structure are sequentially stacked over the substrate”.
In re Claims 22-25: Claims 22-25 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as the claims are understood, Claims 1, 3, 7, 11-12, 14, and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 2016/0379963) in view of Chen et al. (US 2023/0384521).
In re Claim 1, Tsai teaches a method (paragraph 0012) for forming a chip package structure, comprising:
providing (Fig. 1) an electrical substrate 100 (with electrical circuits, paragraph 0014) and a photonic substrate 200 (as being sensitive to a light, paragraph 0021) over and bonded (paragraph 0022) to the electrical substrate 100, wherein
the electrical substrate 100 comprises a first bonding dielectric layer 106 (paragraph 0019),
the photonic substrate 200 comprises a second bonding dielectric layer 206 (paragraph 0023), a dielectric structure 204 (paragraph 0031), a first wiring layer 208a (paragraph 0033),
the dielectric structure 204 is over the second bonding dielectric layer 206,
the first wiring layer 208a is in the dielectric structure 204,
the first wiring layer is in direct contact with the second bonding dielectric layer (e.g., the limitation is omitted from consideration, in accordance with the claim interpretation);
partially removing (Figs. 2-3, paragraphs 0032-0034) the dielectric structure 204 to form a first through hole 304 and a second through hole 302 in the dielectric structure 204, wherein the first through hole 304 passes through the dielectric structure 204 and exposes the first wiring layer 208a; and
forming (Fig. 4, paragraphs 0038-0040) a first conductive via structure 404 and a second conductive via structure 406 in the first through hole 304 and the second through hole 302 respectively, wherein
the first conductive via structure 404 is in direct contact with the first wiring layer 208a, and the second conductive via structure 406 is spaced apart from the first wiring layer 208a.
Tsai does not teach a waveguide structure disposed in the dielectric structure (of the photonic substrate) such that the first wiring layer is between the waveguide structure and the second bonding interface.
Tsai further does not teach first and second bonding pads embedded into the first and second dielectric layers, respectively – e.g., Tsai does not teach a hybrid bonding in which a bonding interface comprises first and second bonding pads and first and second bonding dielectrics.
Chen teaches a photonic substrate (Figs. 2C-4D, paragraph 0005, the photonic substrates may include sensors, Abstract, paragraph 0012), comprising waveguide structures 9 and such semiconductor devices as couplers 8 (paragraphs 0014, 0020) at a surface of substrate 16 of the photonic substrate (paragraphs 0016-0017) in dielectric 23, 26 (paragraphs 0018, 0026), wherein a first wiring layer of an interconnect structure 20 (Fig. 2C, paragraph 0021) is disposed between the waveguide 8 (or 9) and a second bonding dielectric 32 (the number is shown in Figs. 4A-4B, paragraph 0024).
Chen further teaches (Figs. 4C-4D) bonding between the photonic substrate and an electrical substrate 4 (paragraphs 0012), the bonding being a hybrid bonding, in which second bonding pads 34 (embedded in a second bonded dielectric 32, paragraph 0025) are bonded with first bonding pads 34’ (embedded in a first bonded dielectric 32’ of the electrical substrate, paragraph 0029) and the first bonded dielectric is bonded to the second bonded dielectric (paragraphs 0030-0031).
Tsai and Chen teach analogous arts directed to a method for forming a chip package structure comprised bonded together an electrical substrate and a photonic substrate (the photonic substrate comprising sensors), and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Tsai package and the method of its manufacturing in view of the Chen teaching, since they are from the same field of endeavor, and the Chen method created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Tsai package structure and a method
Annotated Modified Fig. 4
PNG
media_image2.png
333
463
media_image2.png
Greyscale
of its manufacturing by adding waveguides (and couplers) near substrate 202 of the photonic substrate and above the top wiring layer, creating by that the first wiring layer being disposed between the second bonding dielectric layer and the waveguide (per Chen), when it is desirable to incorporate light waveguide passages into the photonic substrate, as it is shown in Annotated Modified Annotated Fig. 4, where waveguide as shown as WG and a coupler is shown as CP.
In re Claim 3, Tsai/Chen teaches the method for forming the chip package structure of Claim 1 as cited above.
Tsai/Chen further teaches (Tsai, Fig. 4) that the photonic substrate further comprises a second wiring layer 208c in the dielectric structure 204 and connected between the first wiring layer and the second conductive via structure (e.g., this limitation is omitted from consideration, based on the claim interpretation).
In re Claim 7, Tsai/Chen teaches the method for forming the chip package structure of Claim 1 as cited above.
Tsai/Chen further teaches (Annotated Modified Fig. 4) that the first conductive via structure 404 is longer than the second conductive via structure 406.
In re Claim 10, Tsai/Chen teaches the method for forming the chip package of Claim 1 as cited above, wherein, as is shown for Claim 1, the second bonding dielectric layer is bonded to the first bonding dielectric layer.
In re Claim 11, Tsai teaches a method for forming a chip package structure (paragraph 0012), comprising:
providing (Fig. 1) an electrical substrate 100 (as comprising electrical circuits, paragraphs 0012-0014) and a photonic substrate 200 (as comprising illumination sensors, paragraphs 0012, 0021) over and bonded to the electrical substrate (paragraph 0022), wherein
the electrical substrate 100 comprises
a first bonding dielectric layer 106 (paragraph 0019),
the photonic substrate 200 comprises
a second bonding dielectric layer 206 (paragraph 0023),
the first dielectric structure 204 is over the second bonding dielectric layer 206;
partially removing (Figs. 2-3, paragraphs 0031-0037) the first dielectric structure 204, the second bonding dielectric layer 206, and the first bonding dielectric layer 106 to form a through hole 302 passing through the first dielectric structure 204, the second bonding dielectric layer 206, and the first bonding dielectric layer 106; and
forming (Fig. 4, paragraph 0038) a conductive via structure 404 in the through hole 303.
Tsai does not teach a waveguide structure in the first dielectric structure of the photonic substrate.
Tsai further does not teach a first bonding pad embedded in the first bonding dielectric layer and a second bonding pad embedded in the second bonding dielectric layer, wherein, during the bonding the first bonding pad is bonded with the second bonding pad.
Chen teaches a photonic substrate (Figs. 2C-4D, paragraph 0005, the photonic substrates may include sensors, Abstract, paragraph 0012), comprising waveguide structures 9 and such semiconductor devices as couplers 8 (paragraphs 0014, 0020) at a surface of substrate 16 of the photonic substrate (paragraphs 0016-0017) in dielectric 23, 26 (paragraphs 0018, 0026), wherein a first wiring layer of an interconnect structure 20 (Fig. 2C, paragraph 0021) is disposed between the waveguide 8 (or 9) and a second bonding dielectric 32 (the number is shown in Figs. 4A-4B, paragraph 0024).
Chen further teaches (Figs. 4C-4D) bonding between the photonic substrate and an electrical substrate 4 (paragraphs 0012), the bonding being a hybrid bonding, in which second bonding pads 34 (embedded in a second bonded dielectric 32, paragraph 0025) are bonded with first bonding pads 34’ (embedded in a first bonded dielectric 32’ of the electrical substrate, paragraph 0029) and the first bonded dielectric is bonded to the second bonded dielectric (paragraphs 0030-0031).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Tsai package structure and a method of its manufacturing by adding waveguides (and couplers) near substrate 202 of the photonic substrate and above a top wiring layer of the photonic substrate (per Chen), when it is desirable to incorporate light waveguide passages into the photonic substrate, as it is shown in Annotated Modified Annotated Fig. 4, where a waveguide is shown as WG (and a coupler is shown as CP).
It would have been further obvious for one of ordinary skill in the art before the effective date of filing the application to further modify the Tsai structure and method by substituting the first and second bonding dielectric layers of Tsai with first and second bonding dielectric layers of Chen, each bonding dielectric layer comprising corresponding embedded first (or second) bonding pads, and to conduct bonding between the two substrates by bonding not only dielectrics to each other but also by bonding pads to each other, wherein such bonding dielectric structures are preferred for the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 12, Tsai/Chen teaches the method for forming the chip package structure of Claim 11 as cited above.
Tsai/Chen further teaches that wherein the electrical substrate further comprises (Tsai, Fig. 4 and paragraphs below):
a second dielectric structure – of IMD 104 (paragraph 0016) under the first bonding dielectric layer 106; and
a first wiring layer – comprising elements 108a and 108b (paragraph 0016) and a second wiring layer – comprising element 108c (paragraph 0016) in the second dielectric structure, wherein
the first wiring layer 108a, 108b is between the second wiring layer 108c and the conductive via structure 404, and
the conductive via structure 404 is in direct contact with the first wiring layer 108a.
In re Claim 14, Tsai/Chen teaches the method for forming the chip package structure of Claim 11 as cited above.
Tsai/Chen further teaches (Tsai, Fig. 4 and paragraphs below), that the electrical substrate 100 further comprises:
a second dielectric structure – of IMD 104 (paragraph 0016) under the first bonding dielectric layer 106; and
a wiring layer 108a (paragraph 0016) in the second dielectric structure, wherein
the partially removing of the first dielectric structure 204, the second bonding dielectric layer 106, and the first bonding dielectric layer 206 further comprises:
partially removing the second dielectric structure of 104 over the wiring layer 108a, wherein the through hole 302 (in Fig. 3) further passes through the second dielectric structure over the wiring layer 108a, and the conductive via structure 404 (of Fig. 4) is in direct contact with the wiring layer 108a.
In re Claim 21, Tsai teaches a method for forming a chip package structure (paragraph 0012) comprising:
providing (Fig. 1) an electrical substrate 100 (as comprising electrical circuits, paragraphs 0012-0014) and a photonic substrate 200 (as comprising an imaging device, paragraphs 0020, 0021) over and bonded to the electrical substrate 100 (paragraph 0022), wherein
the electrical substrate 100 comprises a substrate 102 (paragraph 0013), a wiring layer – as one of layers 108i (paragraph 0016), an etch stop layer (between 106 and 104, paragraph 0020 – the etch stop layer is described as not shown in the figures, but described as being used to stop an etching process, and it would have been obvious to place it on top of layer 108a, at which a future created conductive via structure would extend), a first dielectric structure of 104 (paragraph 0020), and a first bonding dielectric 106 (paragraph 0019), the wiring layer, the etch stop layer, the first dielectric structure, and the first bonding pad are sequentially stacked over the substrate (e.g., “the wiring layer, the etch stop layer, and the first bonding dielectric”, in accordance with the claim interpretation) are sequentially stacked over the substrate 102,
the photonic substrate 200 comprises a second bonding dielectric 106 (paragraph 0019), a second dielectric structure of 204 (paragraph 0031),
the second dielectric structure of 204 is over the second bonding dielectric 206;
partially removing (Figs. 2-3, paragraphs 0031-0037) the second dielectric structure of 204, the first dielectric structure – of 104, and the etch stop layer (between 106 and 104 – inherently) to form a through hole 302 continuously passing through the second dielectric structure of 204, the first dielectric structure of 104, and the etch stop layer; and
forming (Fig. 4, paragraphs 0038-0040) a conductive via structure 404 in the through hole 302.
Tsai does not teach that the first and second bonding dielectrics comprising first and second bonding pads, respectively that are bonded together during the bonding process.
Tsai further does not teach that the photonic substrate also comprises a waveguide structure disposed in the second dielectric structure.
Chen teaches a photonic substrate (Figs. 2C-4D, paragraph 0005, the photonic substrates may include sensors, Abstract, paragraph 0012), comprising waveguide structures 9 (and such semiconductor devices as couplers 8, paragraphs 0014, 0020) at a surface of substrate 16 of the photonic substrate (paragraphs 0016-0017) in dielectric 23, 26 (paragraphs 0018, 0026).
Chen further teaches (Figs. 4C-4D) bonding between the photonic substrate and an electrical substrate 4 (paragraphs 0012), the bonding being a hybrid bonding, in which second bonding pads 34 (embedded in a second bonded dielectric 32, paragraph 0025) are bonded with first bonding pads 34’ (embedded in a first bonded dielectric 32’ of the electrical substrate, paragraph 0029) and the first bonded dielectric is bonded to the second bonded dielectric (paragraphs 0030-0031).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Tsai package structure and a method of its manufacturing by adding waveguides (and couplers) near substrate 202 of the photonic substrate (and above a top wiring layer of the photonic substrate per Chen), when it is desirable to incorporate light waveguide passages into the photonic substrate, as it is shown in Annotated Modified Annotated Fig. 4, where a waveguide is shown as WG (and a coupler is shown as CP).
It would have been further obvious for one of ordinary skill in the art before the effective date of filing the application to further modify the Tsai structure and method by substituting the first and second bonding dielectric layers of Tsai with first and second bonding dielectric layers of Chen, each bonding dielectric layer comprising corresponding embedded first (or second) bonding pads, and to conduct bonding between the two substrates by bonding not only dielectrics to each other but also by bonding pads to each other, wherein such bonding dielectric structures are preferred for the manufacturer. See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 22, Tsai/Chen teaches the method for forming the chip package structure of Claim 21 as cited above,
Tsai/Chen further teaches (Annotated Fig. 4) that
the waveguide structure WG (adjacent to and disposed at two sides of the conductive via) has a first surface and a second surface opposite to the first surface (inherently), the first surface faces the electrical substrate 100, and
the conductive via structure 404 extends through the first surface and the second surface.
In re Claim 23, Tsai/Chen teaches the method for forming the chip package structure of Claim 21 as cited above.
Tsai/Chen further teaches (Annotated Modified Fig. 4), that the conductive via structure 404 is a continuous structure (it does not have any breaks between different parts).
In re Claim 24, Tsai/Chen teaches the method for forming the chip package structure of Claim 21 as cited above.
Tsai/Chen further teaches (Annotated Modified Fig. 4), that
an end surface of the conductive via structure 404 is connected to a first surface of the wiring layer 108a of the electrical substrate 100.
In Re Claim 25, Tsai/Chen teaches the method for forming the chip package structure of Claim 24 as cited above, including the conductive via structure and the etch stop layer of the electrical substrate. In view of disposition of the etch stop layer in Claim 21, it would have been obvious for one of ordinary skill in the art before the effective date of filing the application that the end surface of the conductive via structure is substantially level with a second (bottom) surface of the etch stop layer of the electrical substrate.
As far as the claims are understood, Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai/Chen in view of Hsu et al. (US 2015/0380385).
In re Claim 2, Tsai/Chen teaches the method for forming the chip package structure of Claim 1 as cited above.
Tsai/Chen further teaches (see Annotated Modified Fig. 4) that the dielectric structure 204 has a surface facing away from the electrical substrate 100, but does not teach that an end portion of the first conductive via structure 404 – e.g., its part that is in dielectric 204) - is closer to the surface (of 204) than the waveguide structure WG, since the first conductive via structures extends also through an existing substrate 202 of the photonic substrate.
Hsu teaches a package substrate (Fig. 13) and a method of manufacturing the package substrate comprised two bonded substrates 100 and 200 (paragraph 0027), the top substrate 100 being a photonic substrate (as incorporating an image sensor, paragraph 0016) and comprising a via structure 152/154 (paragraphs 0036, 0038), extending through the photonic substrate 100 and a portion of an electronic substrate 200, wherein the photonic substrate does not comprise a substrate layer over its dielectric layer with wires, and, accordingly, the via extends to a top of the dielectric layer.
Tsai/Chen and Hsu teach analogous arts directed to a bonded structure comprised a photonic substrate on an electronic substrate, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Tsai/Chen device and method of Claim 1 in view of the Hsu structure, since they are from the same field of endeavor, and Hsu structure successfully functions.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Tsai/Chen structure created by the method of Claim 1by creating the structure without the substrate layer in the photonic substrate (as is shown in Annotated Modified Fig. 4.1), wherein it is desirable creating a shorter bonded structure:
Annotated Modified Fig. 4.1
PNG
media_image3.png
222
456
media_image3.png
Greyscale
It would have been obvious for one of ordinary skill in the art that in the above structure the end surface (being a top surface) of the first conductive via is closer to the surface of dielectric 204 (that faces away from the circuit substrate 100) than the waveguide WG.
In re Claim 8, Tsai/Chen teaches the method for forming the chip package of Claim 7 as cited above.
Tsai further teaches (Fig. 4) a first surface of the dielectric structure (as a top surface of 204) and a first end surface (as a top surface) of the first conductive via 404 and a second surface (as a top surface) of the second conductive via 406, but does not teach that the first surface of the dielectric structure, the first end surface of the first conductive via structure, and the second end surface of the second conductive via structure are substantially level with each other – his top surfaces of the first and second conductive vias are leveled and are higher than the top surface of the dielectric structure, since both vias extend to a top layer of a substrate 202 of the photonic substrate.
Hsu teaches a package substrate (Fig. 13) and a method of manufacturing the package substrate comprised two bonded substrates 100 and 200 (paragraph 0027), the top substrate 100 being a photonic substrate (as incorporating an image sensor, paragraph 0016) and comprising a via structure 152/154 (paragraphs 0036, 0038), extending through the photonic substrate 100 and a portion of an electronic substrate 200, wherein the photonic substrate does not comprise a substrate layer over its dielectric layer with wires, and, accordingly, the via extends to a top of the dielectric layer.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Tsai/Chen structure created by the method of Claim 1by creating the structure without the substrate layer in the photonic substrate (as is shown in Annotated Modified Fig. 4.1), wherein it is desirable creating a shorter bonded structure:
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application that in the structure of Annotated Modified Fig. 4.1, the top surfaces of the dielectric structure and the first and second conductive vias are leveled with each other.
Allowable Subject Matter
As far as the claims are interpreted, Claim 6 contains allowable subject matter.
Reason for Identification of Allowable Subject Matter
Re Claim 6: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitations of Claim 6 as: “semiconductor structure .. between the first wiring layer and the waveguide structure” and “the first wiring layer is electrically connected to the semiconductor structure”, in combination with other limitations of Claim 6 and with all limitations of Claim 1 (as interpreted), on which Claim 6 depends: Chen, teaching the semiconductor structures as couplers, does not teach that they are between the first wiring layer and the waveguide structure, and does not teach that the first wiring is connected to this semiconductor structure. Yu et al. (US 2020/0006088), also teaching waveguides, does not compensate the deficiency. Additional prior arts of record either cited by this Office Action above or not cited and including Shih et al. (US 2023/0369264), Chen et al. (US 2021/0313254), or Shih et al. (US 2022/0139805) – do not compensate for the above deficiency.
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center - for more information about Patent Center and visit https://www.uspto.gov/patents/docx - for information about filing in DOCX format.
For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 06/25/26
Prosecution Insights