DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (drawn to claims 1-15) in the reply filed on 02 August 2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “pair of gate sidewall spacers on opposite sidewalls of the sacrificial gate structure,” of claim 7 must be shown or the feature(s) canceled from the claim(s). Figures 6A, 7A, 8A illustrate a sacrificial gate structure 50 (para. 40) which comprises the gate sidewall spacers 55. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 22 objected to because of the following informalities: the last lines of claim 22 recite the phrase, “of the first gate structure; ” which contains a grammatical error in the punctuation concluding this last phrase of the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Examiner has unresolved questions regarding “forming a source/drain epitaxial layer over a source/drain region of the fin structure” of claim 1 (and by dependency claims 2-11). The specification describes this feature by specifying that the “S/D epitaxial layer 60A includes one or more layers of Si, SiGe and SiGeP for a p-channel FET” and the “S/D epitaxial layer 60B includes one or more layers of Si, SiP, SiC and SiCP for an n-channel FET” in paragraph 50 of the specification. FIG. 8A and FIG. 8E show the source/drain epitaxial layer 60A and source/drain epitaxial layer 60B being formed on the protection layers 25a, 25d and channel layer 25b of the multi-film layer 25 while not being formed on the lower fin structure 11 formed from substrate 10. The specification further specifies that the substrate is formed of crystalline semiconductor material such as crystalline Si. The examiner’s unresolved questions regarding “forming a source/drain epitaxial layer over a source/drain region of the fin structure” include the following: How do you form an epitaxial S/D region on exposed portions of multi-film layers 25 without forming the epitaxial S/D region on exposed portions of the lower fin structure? How do you form an epitaxial S/D region on exposed portions of multi-film layers 25 without forming the epitaxial S/D region on exposed portions of the substrate?
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites the limitation "on the first ends of the sacrificial layer " in line 5 of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 23 also recites the limitation “the inner spacer” in both lines 4 and 5 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this office action, the limitation “the inner spacer” is interpreted to have the following meaning: the inner spacers.
Claim 24 recites the limitation "wherein the inner spacers" in line 1 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this office action, the limitation is interpreted to have the following meaning: wherein inner spacers.
Claim 25 recites the limitation " by the inner spacers" in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this office action, the limitation is interpreted to have the following meaning: by inner spacers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 12-15, and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Penumatcha et al. (US PGPub 20220199783 A1; hereinafter referred to as "Penumatcha”) in view of Park et al. (US PGPub 20240006522 A1; hereinafter referred to as "Park”) .
Re claim 1: Penumatcha teaches a method of manufacturing a semiconductor device, comprising: forming a fin structure (FIG. 4B; para. 82) comprising a lower fin structure (FIG. 4B| lower fin structure formed of lower portion of layer 402A) and an upper fin structure (FIG. 4B| upper fin structure formed of layers of the fin extending above layer 402A and including the upper portion of layer 402A) disposed over the lower fin structure (FIG. 4B), the upper fin structure comprising dielectric layers (FIG. 4B: el. 402A, 402B, 402C; para. 80) and channel layers (FIG. 4B: el. 404A, 404B; para. 81) alternately stacked (FIG. 4B); forming a sacrificial gate structure over the upper fin structure (FIG. 4C: el. 408; para. 83); forming a source/drain epitaxial layer over a source/drain region of the fin structure after forming the sacrificial gate structure over the upper fin structure (FIG. 10: el. 424; para. 104-105| epitaxial conductive material layer forms first layer of the source/drain 424); removing the sacrificial gate structure (FIG. 8A; para. 18); removing the dielectric layers after removing the sacrificial gate structure (para. 18; FIG. 8A| removing the sacrificial gate structure 408 exposes dielectric layers 402A, 402B, and 402C which are then also removed); and forming a gate structure around the channel layers (FIG. 9A: el. (418, 422); para. 20, 99). The embodiment of FIG. 4B – FIG. 10 of Penumatcha fails to disclose the upper fin structure comprising dielectric layers and multi-film layers alternately stacked, wherein each of the multi-film layers comprises a channel layer, a first protection layer and a second protection layer, and the channel layer is between the first protection layer and the second protection layer; removing the sacrificial gate structure after forming the source/drain epitaxial layer; and forming a gate structure around the multi-film layers.
Penumatcha teaches another embodiment as depicted in FIG. 2 and FIG. 11 which teaches the upper fin structure comprising dielectric layers (FIG. 11: el. 402A, 402B, 402C; para. 109-111, 80) and multi-film layers (FIG. 11: el. (1103, 404A, 1103), (1103, 404B, 1103); para. 109-111) alternately stacked (FIG. 11), wherein each of the multi-film layers comprises a channel layer (FIG. 11: el. 404A, 404B; para. 111, 81), a first protection layer (FIG. 11: el. 1103; para. 109| first protection layer formed from the protection layers 1103 contacting the bottom side of channel layers 404A and 404B) and a second protection layer (FIG. 11: el. 1103; para. 109| second protection layer formed from the protection layers 1103 contacting the top side of channel layers 404A and 404B), and the channel layer is between the first protection layer and the second protection layer (FIG. 11: el. (1103, 404A, 1103), (1103, 404B, 1103)); and forming a gate structure around the multi-film layers (FIG. 2: el. (122, 124); para. 73, FIG. 3: el. 360; para. 75). Penumatcha also teaches a benefit of multi-film layers including buffering protection layers adjacent to the channel layers is protection of the channel layers during processing steps, as well as improved charge transport and reduced self-heating (para. 74, 109).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the embodiments of Penumatcha, to enable using the multi-film layers of an embodiment of Penumatcha in the semiconductor device of another embodiment of Penumatcha, for the benefit of protection of the channel layers during processing steps, as well as improved charge transport and reduced self-heating (para. 74, 109).
Penumatcha teaches removing the sacrificial gate structure but fails to teach removing the sacrificial gate structure after forming the source/drain epitaxial layer.
In a similar field of endeavor, Park teaches a method of forming a semiconductor device comprising forming a fin structure and teaches removing the sacrificial gate structure after forming the source/drain epitaxial layer (FIG. 9G – FIG. 9I: el. 120, 150; para. 83, 85). It would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Penumatcha and Park, to enable using the sequence of removing the sacrificial gate structure after forming the source/drain epitaxial layer because the selection of a known sequence of operations based on its suitability for its intended use supports a prima facie case of obviousness.
Re claim 2: The combination of Penumatcha and Park teaches the method of claim 1 further comprising: forming an isolation insulating layer (Penumatcha - FIG. 5A: el. 410; para. 84) around the lower fin structure after forming the fin structure.
Re claim 3: The combination of Penumatcha and Park teaches the method of claim 1, wherein forming the fin structure comprises: forming stacked layers (Penumatcha - FIG. 4A: 120, 118, 402A, 404A, 402B, 404B, 402C); over a substrate (Penumatcha - FIG. 4A: el. 102; para. 71); and patterning the stacked layers and the substrate to form the fin structure comprising the lower fin structure and the upper fin structure (Penumatcha - FIG. 4B; para. 82).
Re claim 4: The combination of Penumatcha and Park teaches the method of claim 1, wherein sidewalls of the channel layer are revealed after removing the sacrificial gate structure (Penumatcha - FIG. 8A-8B: el. 404B| sidewalls of channel layer 404B are exposed in the y-direction as seen in FIG. 8A and FIG. 8B after removing the sacrificial gate structure 408 depicted in FIG. 7B, 5B).
Re claim 5: The combination of Penumatcha and Park teaches the method of claim 1, wherein a bottom surface of the channel layer is covered by the first protection layer, and a top surface of the channel layer is covered by the second protection layer after removing the dielectric layers (Penumatcha – FIG 2: el. 106, 202; para. 72-73, 109| FIG. 11 teaches that the film stack for forming the device of FIG. 2 is formed with buffer protection layers adjacent to the channel layers; FIG. 2 shows that first and second buffer protection layers 202 cover the bottom and top surface of the channel layers 104 and 106 through-out processing of device including at the end of processing the device, which is after removing the dielectric layers).
Re claim 6: The combination of Penumatcha and Park teaches the method of claim 1, wherein forming the gate structure comprises: forming a gate dielectric layer around the multi-film layers; and forming a gate electrode layer over the gate dielectric layer (Penumatcha – FIG. 9A: el. 418, 422; para. 20, 99).
Re claim 7: The combination of Penumatcha and Park teaches the method of claim 1 further comprising: forming a pair of gate sidewall spacers on opposite sidewalls of the sacrificial gate structure (Penumatcha – FIG. 7A: el. 114; para. 92| gate sidewall spacers formed of spacers 114 adjacent to first gate structure 408).
Re claim 8: The combination of Penumatcha and Park teaches the method of claim 7, wherein the source/drain epitaxial layer is formed over the source/drain region of the fin structure after forming the pair of gate sidewall spacers (Penumatcha – FIG. 10: el. 424; para. 104-105, FIG. 7A: el. 114| epitaxial conductive material layer forms first layer of the source/drain 424 and is formed after gate sidewall spacers 114 are formed adjacent to sacrificial gate structure 408), and forming the source/drain epitaxial layer comprises: partially removing the dielectric layers to reduce lengths of the dielectric layers such that first ends of the dielectric layers are located under the pair of gate sidewall spacers (Penumatcha – FIG. 6A-7A; para. 13, 87| sacrificial layers 402A and 402B are partially removed such that first ends of the sacrificial layers are located under gate sidewall spacers 114 (spacers 114 adjacent to first gate structure 408) as shown in FIG. 7A); forming inner spacers on the first ends of the dielectric layers (Penumatcha – FIG. 7A: el. 114| inner spacers formed of spacers 114 adjacent to dielectric layers 402A and 402B (formed in spaces 411B, 411C, 413B, and 413C of FIG. 6B)), wherein second ends of the multi-film layers laterally protrude from the inner spacers after forming the inner spacers on the first ends of the dielectric layers (Penumatcha – FIG. 7A-10, FIG. 2| second ends of channel layers 404A and 404B laterally protrude from the inner spacers 114 (inner spacers 114 described in previous limitation) in FIG. 7A-10 after forming the inner spacer, and in the combination of embodiments of Penumatcha as defined in Re claim 1 section, the multi-film layers laterally protrude from the inner spacers after forming the inner spacers on the first ends of the dielectric layers as shown in FIG. 2); and forming the source/drain epitaxial layer to cover the inner spacers and the second ends of the multi-film layers (Penumatcha – FIG. 10: el. 424, FIG. 2: el. 108; para. 104-105| source/drain epitaxial layer formed to cover inner spacers 114, and in the combination of embodiments of Penumatcha as defined in Re claim 1 section, also cover the multi-film layers as shown in FIG. 2).
Re claim 12: Penumatcha teaches a method of manufacturing a semiconductor device, comprising: forming a fin structure (FIG. 4B; para. 82) comprising sacrificial layers (FIG. 4B: el. 402A, 402B, 402C; para. 80, 15, 18) and channel layers (FIG. 4B: el. 404A, 404B; para. 81) alternately stacked (FIG. 4B); forming a first gate structure over the fin structure (FIG. 4C: el. 408; para. 83); forming gate sidewall spacers on opposite sidewalls of the first gate structure (FIG. 7A: el. 114; para. 92| gate sidewall spacers formed of spacers 114 adjacent to first gate structure 408); forming a source/drain epitaxial layer at opposite sides of the first gate structure and the gate sidewall spacers (FIG. 10: el. 424; para. 104-105| epitaxial conductive material layer forms first layer of the source/drain 424); removing the first gate structure (FIG. 8A; para. 18); removing the sacrificial layers after removing the first gate structure (para. 18; FIG. 8A| removing the first gate structure 408 exposes sacrificial layers 402A, 402B, and 402C which are then also removed); and forming a second gate structure around the channel layers (FIG. 9A: el. (418, 422); para. 20, 99). The embodiment of FIG. 4B – FIG. 10 of Penumatcha fails to disclose a fin structure comprising sacrificial layers and multi-film layers alternately stacked, wherein each of the multi-film layers comprises a channel layer, a first protection layer and a second protection layer, and the channel layer is between the first protection layer and the second protection layer; removing the first gate structure after forming the source/drain epitaxial layer; and forming a second gate structure around the multi-film layers.
Penumatcha teaches another embodiment as depicted in FIG. 2 and FIG. 11 which teaches forming a fin structure comprising sacrificial layers (FIG. 11: el. 402A, 402B, 402C; para. 109-111, 80, 15) and multi-film layers (FIG. 11: el. (1103, 404A, 1103), (1103, 404B, 1103); para. 109-111) alternately stacked (FIG. 11), wherein each of the multi-film layers comprises a channel layer (FIG. 11: el. 404A, 404B; para. 111, 81), a first protection layer (FIG. 11: el. 1103; para. 109| first protection layer formed from the protection layers 1103 contacting the bottom side of channel layers 404A and 404B) and a second protection layer (FIG. 11: el. 1103; para. 109| second protection layer formed from the protection layers 1103 contacting the top side of channel layers 404A and 404B), and the channel layer is between the first protection layer and the second protection layer (FIG. 11: el. (1103, 404A, 1103), (1103, 404B, 1103)); and forming a second gate structure around the multi-film layers (FIG. 2: el. (122, 124); para. 73, FIG. 3: el. 360; para. 75). Penumatcha also teaches a benefit of multi-film layers including buffering protection layers adjacent to the channel layers is protection of the channel layers during processing steps, as well as improved charge transport and reduced self-heating (para. 74, 109).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the embodiments of Penumatcha, to enable using the multi-film layers of an embodiment of Penumatcha in the semiconductor device of another embodiment of Penumatcha, for the benefit of protection of the channel layers during processing steps, as well as improved charge transport and reduced self-heating (para. 74, 109).
Penumatcha teaches removing the first gate structure but fails to teach removing the first gate structure after forming the source/drain epitaxial layer.
In a similar field of endeavor, Park teaches a method of forming a semiconductor device comprising forming a fin structure and teaches removing the first gate structure after forming the source/drain epitaxial layer (FIG. 9G – FIG. 9I: el. 120, 150; para. 83, 85). It would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Penumatcha and Park, to enable using the sequence of removing the sacrificial gate structure after forming the source/drain epitaxial layer because the selection of a known sequence of operations based on its suitability for its intended use supports a prima facie case of obviousness.
Re claim 13: The combination of Penumatcha and Park teaches the method of claim 12, wherein forming the source/drain epitaxial layer comprises: partially removing the sacrificial layers to reduce lengths of the sacrificial layers such that first ends of the sacrificial layers are located under the gate sidewall spacers (Penumatcha – FIG. 6A-7A; para. 13, 87| sacrificial layers 402A and 402B are partially removed such that first ends of the sacrificial layers are located under gate sidewall spacers 114 (spacers 114 adjacent to first gate structure 408) as shown in FIG. 7A); forming inner spacers on the first ends of the sacrificial layers (Penumatcha – FIG. 7A: el. 114| inner spacers formed of spacers 114 adjacent to dielectric layers 402A and 402B (formed in spaces 411B, 411C, 413B, and 413C of FIG. 6B)), wherein second ends of the multi-film layers laterally protrude from the inner spacers after forming the inner spacers on the first ends of the sacrificial layers (Penumatcha – FIG. 7A-10, FIG. 2| second ends of channel layers 404A and 404B laterally protrude from the inner spacers 114 (inner spacers 114 described in previous limitation) in FIG. 7A-10 after forming the inner spacers, and in the combination of embodiments of Penumatcha as defined in Re claim 12 section, the multi-film layers laterally protrude from the inner spacers after forming the inner spacers on the first ends of the dielectric layers as shown in FIG. 2); and forming the source/drain epitaxial layer to cover the inner spacers and the second ends of the multi-film layers (Penumatcha – FIG. 10: el. 424, FIG. 2: el. 108; para. 104-105| source/drain epitaxial layer formed to cover inner spacers 114, and in the combination of embodiments of Penumatcha as defined in Re claim 12 section, also cover the ends of the multi-film layers as shown in FIG. 2).
Re claim 14: The combination of Penumatcha and Park teaches the method of claim 13, wherein the inner spacers are in contact with the first protection layer and the second protection layer (Penumatcha – FIG. 7A: el. 114, FIG. 2| inner spacers, formed of spacers 114 adjacent to dielectric layers 402A and 402B (formed in spaces 411B, 411C, 413B, and 413C of FIG. 6B), are in contact with the channel layer 404A through liner 116 in FIG. 7A-10, and in the combination of embodiments of Penumatcha as defined in Re claim 12 section, the inner spacers 114 are in contact with the first bottom protection layer 202 of the channel layer and the second top protection layer 202 of the channel layer through liner 116, as shown in FIG. 2).
Re claim 15: The combination of Penumatcha and Park teaches the method of claim 13, wherein the source/drain epitaxial layer is spaced apart from the first gate structure by the inner spacers before removing the first gate structure (Penumatcha – FIG. 7A, 10, Park - para. 83, 85| Penumatcha teaches first gate structure 408 spaced laterally apart from the region where the source/drain structure will be formed in area 410 by the inner spacers 114 (inner spacers 114 described in Re claim 13 section) as shown in FIG. 7A, and Park teaches forming the source/drain epitaxial layer before removing the first gate structure, as described in Re Claim 12 section).
Re claim 21: Penumatcha teaches a method of manufacturing a semiconductor device, comprising: forming a film stack (FIG. 4A-4B; para. 76, 79, 82) comprising a first channel layer (FIG. 4B: el. 404A; para. 81), a second channel layer (FIG. 4B: el. 404B; para. 81) over the first channel layer and a sacrificial layer (FIG. 4B: el. 402B; para. 80, 15, 18) interposed between the first channel layer and the second channel layer (FIG. 4B); forming a first gate structure over the film stack (FIG. 4C: el. 408; para. 83); partially removing the sacrificial layer such that a first lateral dimension of the sacrificial layer is smaller than a second lateral dimension of the first multi-film layer and the second multi-film layer (FIG. 6A; para. 13, 87); forming a source/drain epitaxial layer at opposite sides of the first gate structure (FIG. 10: el. 424; para. 104-105| epitaxial conductive material layer forms first layer of the source/drain 424); replacing the first gate structure with a second gate structure (FIG. 8A; para. 18, FIG. 9A: el. (418, 422); para. 20, 99), wherein the sacrificial layer is removed after the first gate structure is removed and before the second gate structure is formed (para. 18; FIG. 8A| removing the first gate structure 408 exposes sacrificial layers 402A, 402B, and 402C which are then also removed before the second gate structure (418, 422) is formed). The embodiment of FIG. 4B – FIG. 10 of Penumatcha fails to disclose a film stack comprising a first multi-film layer, a second multi-film layer over the first multi-film layer and a sacrificial layer interposed between the first multi-film layer and the second multi-film layer, wherein the first multi-film layer comprises a first protection layer, a second protection layer and a channel layer between the first protection layer and the second protection layer; and after forming the source/drain epitaxial layer, replacing the first gate structure with a second gate structure.
Penumatcha teaches another embodiment as depicted in FIG. 2 and FIG. 11 which teaches forming a film stack comprising a first multi-film layer (FIG. 11: el. (1103, 404A, 1103); para. 109-111), a second multi-film layer (FIG. 11: el. (1103, 404B, 1103); para. 109-111) over the first multi-film layer and a sacrificial layer (FIG. 11: el. 402B; para. 109-111, 80, 15) interposed between the first multi-film layer and the second multi-film layer (FIG. 11), wherein the first multi-film layer comprises a first protection layer (FIG. 11: el. 1103; para. 109| first protection layer 1103 contacting the bottom side of channel layer 404A), a second protection layer (FIG. 11: el. 1103; para. 109| second protection layer 1103 contacting the top side of channel layer 404A) and a channel layer (FIG. 11: el. 404A) between the first protection layer and the second protection layer (FIG. 11). Penumatcha also teaches a benefit of multi-film layers including buffering protection layers adjacent to the channel layers is protection of the channel layers during processing steps, as well as improved charge transport and reduced self-heating (para. 74, 109).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the embodiments of Penumatcha, to enable using the multi-film layers of an embodiment of Penumatcha in the semiconductor device of another embodiment of Penumatcha, for the benefit of protection of the channel layers during processing steps, as well as improved charge transport and reduced self-heating (para. 74, 109).
Penumatcha teaches replacing the first gate structure with a second gate structure but fails to teach after forming the source/drain epitaxial layer, replacing the first gate structure with a second gate structure.
In a similar field of endeavor, Park teaches a method of forming a semiconductor device comprising forming a fin structure including a film stack and teaches after forming the source/drain epitaxial layer, replacing the first gate structure with a second gate structure (FIG. 9G – FIG. 9I: el. 120, 150; para. 83, 85). It would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Penumatcha and Park, to enable using the sequence of removing the sacrificial gate structure after forming the source/drain epitaxial layer because the selection of a known sequence of operations based on its suitability for its intended use supports a prima facie case of obviousness.
Re claim 22: The combination of Penumatcha and Park teaches the method of claim 21 further comprising: before forming the source/drain epitaxial layer at the opposite sides of the first gate structure, forming gate sidewall spacers on opposite sidewalls of the first gate structure (Penumatcha - FIG. 7A: el. 114; para. 92| gate sidewall spacers formed of spacers 114 adjacent to first gate structure 408, and gate sidewall spacers 114 are formed before forming either the source/drain epitaxial layer or the second gate structure).
Re claim 23: The combination of Penumatcha and Park teaches the method of claim 22, wherein forming the source/drain epitaxial layer comprises: forming inner spacers on the ends of the sacrificial layer (Penumatcha – FIG. 7A: el. 114| inner spacers formed of spacers 114 adjacent to dielectric layers 402A and 402B (formed in spaces 411B, 411C, 413B, and 413C of FIG. 6B)), wherein ends of the first and second multi-film layers laterally protrude from the inner spacers after forming the inner spacers on the first ends of the sacrificial layer (Penumatcha – FIG. 7A-10, FIG. 2| ends of first and second channel layers 404A and 404B laterally protrude from the inner spacers 114 (inner spacers 114 described in previous limitation) in FIG. 7A-10 after forming the inner spacers, and in the combination of embodiments of Penumatcha as defined in Re claim 21 section, the first and second multi-film layers laterally protrude from the inner spacers after forming the inner spacers on the first ends of the dielectric layers as shown in FIG. 2); and forming the source/drain epitaxial layer to cover the inner spacers and the ends of the first and second multi-film layers (Penumatcha – FIG. 10: el. 424, FIG. 2: el. 108; para. 104-105| source/drain epitaxial layer formed to cover inner spacers 114, and in the combination of embodiments of Penumatcha as defined in Re claim 21 section, also cover the ends of the first and second multi-film layers as shown in FIG. 2).
Re claim 24: The combination of Penumatcha and Park teaches the method of claim 21, wherein inner spacers are in contact with the first protection layer and the second protection layer of the first multi-film layer (Penumatcha – FIG. 7A: el. 114, FIG. 2| inner spacers, formed of spacers 114 adjacent to dielectric layers 402A and 402B (formed in spaces 411B, 411C, 413B, and 413C of FIG. 6B), are in contact with the channel layer 404A through liner 116 in FIG. 7A-10, and in the combination of embodiments of Penumatcha as defined in Re claim 21 section, inner spacers 114 are in contact with the first bottom protection layer 202 of the channel layer and the second top protection layer 202 of the channel layer through liner 116, as shown in FIG. 2).
Re claim 25: The combination of Penumatcha and Park teaches the method of claim 21 wherein the source/drain epitaxial layer is spaced apart from the first gate structure by inner spacers before removing the first gate structure (Penumatcha – FIG. 7A, 10, Park - para. 83, 85| Penumatcha teaches first gate structure 408 spaced laterally apart from the region where the source/drain structure will be formed in area 410 by inner spacers 114 as shown in FIG. 7A, and Park teaches forming the source/drain epitaxial layer before removing the first gate structure, as described in Re Claim 21 section).
Allowable Subject Matter
Claims 9, 10, and 11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 9: The closest prior art, Penumatcha'783 and Park’522, either alone or in combination fails to disclose or suggest, “wherein the first protection layer comprises a first etch resistive layer, removing the dielectric layers comprises an etching process, the etching process has a first etch rate to the first etch resistive layer and a second etch rate to the channel layer, and the first etch rate is less than the second etch rate,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 10: The closest prior art, Penumatcha'783 and Park’522, either alone or in combination fails to disclose or suggest, “wherein the first protection layer comprises a first etch resistive layer, removing the dielectric layers comprises an etching process, the etching process has a first etch rate to the first etch resistive layer and a second etch rate to the channel layer, and the first etch rate is less than the second etch rate,” in combination with the additionally claimed features, as claimed by the applicant.
Re claim 11: The closest prior art, Penumatcha'783 and Park’522, either alone or in combination fails to disclose or suggest, “partially removing the dielectric layers to reduce widths of the dielectric layers before the sacrificial gate structure is formed over the upper fin structure,” in combination with the additionally claimed features, as claimed by the applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art made of record and not relied upon teaches forming gate-all-around semiconductor devices formed from a material stack comprising channel protection layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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