Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Invention I (Claims 1-9 readable thereon) in the reply filed on April 29, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Oh et al (USPGPUB 20250120140, hereinafter “Oh”).
Regarding Claim 1, Oh teaches (Fig. 3A) A semiconductor device, comprising: a substrate (102); two gate structures (160M) disposed on (two gate structures 160M are seen disposed on substrate 102) the substrate (102); a spacer structure (structure of layers 118, 142, 144, hereinafter SP) disposed on (spacer structure SP is seen disposed on substrate 102) the substrate (102) and surrounding (spacer structure SP is seen) each of the gate structures (160M); an epitaxial structure (130) disposed in (epitaxial structure 130 is seen disposed in substrate 102) the substrate (102), between (epitaxial structures 130 are seen between two gate structures 160M) the two gate structures (160M); a capping structure (CA) disposed on (capping structure CA is disposed on the epitaxial structure 130) the epitaxial structure (130), between (capping structure CA is disposed between the two gate structures 160M) the two gate structures (160M); and a metal silicide layer (172), disposed on (metal silicide layer 172 is seen disposed on the bottom of, and in contact with, capping structure CA) the capping structure (CA); wherein the spacer structure (SP) comprises a first spacer (118), a second spacer (142) and a third spacer (144) stacked sequentially on a sidewall of (spacer elements 118, 142, 144 of the spacer structure are stacked sequentially on a sidewall of the gate structure 160M) each of the gate structures (160M), and the second spacer (142) at least contacts (second spacer 142 is seen contacting a portion of a sidewall of capping structure CA) a portion of a sidewall of the capping structure (CA).
Regarding Claim 3, Oh teaches (Fig. 3A) the semiconductor device according to claim 1, wherein the second spacer (142) comprises a stripe-shaped cross-section disposed on (second spacer 142 is seen having a stripe-shaped cross-section, which is on a top surface of substrate 102) a top surface of the substrate (102).
Regarding Claim 4, Oh teaches (Fig. 3A) the semiconductor device according to claim 3, wherein the third spacer (144) overlays another portion of (144 is seen overlaying a portion of the capping layer CA’s sidewall which is not in contact with the sidewall of capping structure CA) the sidewall of the capping structure (CA).
Regarding Claim 5, Oh teaches (Fig. 3A) the semiconductor device according to claim 1, wherein the second spacer (142) comprises a material different from ([0050], “the insulating liner 142 may include, but is not limited to, silicon nitride (SiN), SiCN, SiBN, SiON, SiOCN, SiBCN, and/or a combination thereof”; [0050], “the inter-gate dielectric 144 may include, but is not limited to, a silicon oxide film”; [0039], “The insulating spacer 118 may include, for example, silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, and/or a combination thereof”; an embodiment exists wherein the second spacer 142 is made of silicon nitride, and third spacer 144 and first spacer 118 are made of silicon oxide) materials of the first spacer (118) and the third spacer (144).
Regarding Claim 6, Oh teaches (Fig. 3A) the semiconductor device according to claim 1, wherein an aspect ratio between a thickness of the capping structure (CA) and a minimum distance from (as seen in Fig. 3A, there is a tapering structure so there is a variety of thicknesses attributable to capping structure CA, and a minimum distance (w1 of annotated figure 3A of Oh below) between the capping structure CA and one of the two gate structures 160M is seen to be approximately 1.2-2.0 times a thickness (w2 of the annotated figure below) of one of the two gate structures 160M) the capping structure (CA) to one of the two gate structures (160M) is 1.2 to 2.2.
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Regarding Claim 7, Oh teaches (Fig. 3A) the semiconductor device according to claim 1, wherein the capping structure (CA) comprises a first capping layer (176) and a second capping layer (174) stacked sequentially on (the first capping layer 176 and the second capping layer 174 are seen stacked sequentially on the epitaxial structure 130) the epitaxial structure (130).
Regarding Claim 9, Oh teaches (Fig. 3A) the semiconductor device according to claim 1, wherein the semiconductor device comprises a static random access memory device ([0023], “In some embodiments, the first device area A1 may be an area constituting a volatile memory device, such as dynamic random access memory (DRAM) or static RAM (SRAM)…”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oh as applied to claim 7 above, and further in view of Kawamura et al (USPGPUB 20080265417, hereinafter “Kawamura”).
Regarding Claim 8, Oh teaches the semiconductor device according to claim 7, but is silent with regards to a device wherein the second capping layer comprises a thickness between 130 angstroms to 210 angstroms.
Kawamura teaches a device wherein the second capping layer comprises a thickness between 130 angstroms to 210 angstroms ([0078], “a tantalum (Ta) layer is formed as a barrier metal layer 42 on the Ti layer 41 by the sputtering to have a thickness of 1 nm to 20 nm, e.g., 15 nm”; A thickness of 15 nm, or 150 Angstroms, is within the range described ).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the dimensions of Kawamura into the device of Oh in order to arrive at the expected result of creating a device which follows conventional sizing standards, allowing for the known benefit of increased compatibility and ability to be integrated with other contemporarily available devices with reasonable expectation of success.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, the closest available references, that of Oh, alone or in reasonable combination with any other available reference, fails to teach the limitation, “the second spacer comprises a L-shaped cross-section, and a vertical portion of the L-shaped cross-section overlays a whole sidewall of the capping structure” (The L-shaped cross-section of the second spacer 142 is not seen overlaying the entire sidewall of the capping structure CA, as the capping structure vertically extends beyond the capping structure, and no available reference would reasonably motivate an alteration to the dimensions of the second spacer 142).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR J LASASSO whose telephone number is (703)756-5668. The examiner can normally be reached M-F 8-5 EST.
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/V.J.L./Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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