DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-18, in the reply filed on May 5, 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 6, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-7, 10, 11, 14, 15, 21, and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al (US Pub 2022/0392889).
In re claim 1, Lin et al discloses a semiconductor device, comprising: a substrate (i.e. 50); a transistor (i.e. 119) comprising a gate electrode (i.e. 94) on the substrate, wherein the gate electrode comprises a gate electrode material; a capacitor structure, comprising: a first electrode (i.e. 95A) and a second electrode (i.e. 95B) on the substrate, wherein the first electrode and the second electrode comprise the gate electrode material; a plurality of first conductive features (i.e. 111A) disposed over the first electrode, wherein each of the plurality of first conductive features is tapered toward the substrate; a plurality of conductive vias (i.e. 117A), each of which is disposed over a corresponding one of the plurality of first conductive features, wherein each of the plurality of conductive vias is tapered toward the substrate; and a third electrode (i.e. 116A) over the plurality of conductive vias, wherein the third electrode is electrically connected to the first electrode through the plurality of first conductive features and the plurality of conductive vias (i.e. see at least Figures 26A, 26B, 27).
In re claim 5, Lin et al discloses wherein the third electrode comprises a material different from the gate electrode material (i.e. see at least paragraph 0072).
In re claim 6, Lin et al discloses wherein a lateral surface of each of the conductive vias and a lateral surface of the corresponding one of the plurality of first conductive features are discontinuous (i.e. see at least Figures 26A, 26B, 27).
In re claim 7, Lin et al discloses wherein the first electrode is free from vertically overlapping the third electrode (i.e. see at least Figures 26A, 26B, 27),
In re claim 10, Lin et al discloses a semiconductor device, comprising: a substrate (i.e. 50); a capacitor structure on the substrate, comprising: a first electrode (i.e. 95A) and a second electrode (i.e. 95B) exhibiting a parallel capacitor, wherein the first electrode comprises a plurality of fingers extending along a first direction; a third electrode (i.e. 116A or 116B) electrically connected to the first electrode and comprising a plurality of fingers extending along the first direction, wherein the plurality of fingers of the first electrode is free from vertically overlapping the plurality of fingers of the third electrode (i.e. see at least Figure 28).
In re claim 11, Lin et al discloses wherein the third electrode (i.e. 116B) at least partially overlaps the second electrode (i.e. see at least Figure 28).
In re claim 14, Lin et al discloses further comprising: a transistor (i.e. 119) comprising a gate electrode (i.e. 94) disposed on the substrate, wherein a material of the gate electrode is the same as that of the first electrode (i.e. see at least Figures 26A, 26B, 27).
In re claim 15, Lin et al discloses wherein a material of the first electrode is different from that of the third electrode (i.e. see at least paragraph 0072).
In re claim 21, Lin et al discloses a semiconductor device, comprising: a substrate (i.e. 50), comprising a first region and a second region; a gate dielectric layer (i.e. 92) on the first region the substrate; a gate structure (i.e. 94) on the gate dielectric layer; a dielectric layer (i.e. 88) on the second region the substrate; a capacitor structure on the second region of the substrate and comprising a first electrode (i.e. 95A) and a second electrode (i.e. 95B) defining a parallel capacitor, wherein the first electrode has a portion surrounded by the dielectric layer, and the dielectric layer has a material the same as a material of the gate dielectric layer (i.e. see at least Figures 26A, 26B, 27).
In re claim 22, Lin et al discloses further comprising: an interlayer dielectric (ILD) layer (i.e. 108 or 114) covering the first region and the second region of the substrate, wherein the portion of the first electrode is spaced apart from the ILD layer by the dielectric layer (i.e. see at least Figures 26A, 26B, 27).
Allowable Subject Matter
Claims 2-4, 8, 9, 12, 13, and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
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/ANTHONY HO/Primary Examiner, Art Unit 2817
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