DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
The control circuit “130” in paragraph [0028], line 11 is not shown in Fig. 2.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The recitation of “wherein the bit line as a third segment coupled to a third portion of the memory cells” in claim 6, lines 1-2 is unclear. How can the bit line be a third segment?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Young et al. (US 12,302,557, hereinafter “Young”).
Regarding claim 1, Young discloses a semiconductor device, comprising:
a memory array (Figs. 1B and 1C) comprising a plurality of memory cells arranged in a row; and
an interconnect structure disposed over the memory cells (column 3, lines 32-33) and comprising a bit line, wherein the bit line is coupled to each of the memory cells arranged in the row (Fig. 1C), wherein the bit line has a first segment (claim 1, column 21, lines 22-23, the first portion) coupled to a first portion of the memory cells and a second segment (claim 1, lines 23-24, one of the other portions) coupled to a second portion of the memory cells, and wherein the first segment has a first width and the second segment has a second width that is smaller than the first width.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5, 8 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Young et al.
The only differences between claims 2-5, 8 and 18-20 and Young et al. are the recitation of specific numbers of memory cells and specific locations of the first and second portions. It would have been a matter of design choice to use specific numbers of memory cells and specific locations for the first and second portions since Applicant has not disclosed the use of specific numbers of memory cells and specific locations for the first and second portions solves aby stated problem and it appears that the semiconductor device would perform well with the numbers of memory cells and locations of the first and second portions of Young.
Allowable Subject Matter
Claims 11-17 are allowed.
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the logic circuit is a first logic circuit, the semiconductor device further comprising: a second logic circuit disposed by the memory array and coupled to the memory cells arranged in the row, wherein: the first logic circuit and the second logic circuit sandwich the memory array along a lengthwise direction of the row, the bit line has a third segment coupled to a third portion of the memory cells, the third portion of the memory cells are located closer to the second logic circuit than the first portion of the memory cells, and the third segment has a third width that is equal to the first width.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 10, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “wherein the interconnect structure further comprises a complimentary bit line coupled to each of the memory cells arranged in the row, wherein the complimentary bit line has a first segment coupled to the first portion of the memory cells and a second segment coupled to the second portion of the memory cells, and wherein the first segment of the complimentary bit line is narrower than the second segment of the complimentary bit line.” in combination with the other limitations thereof as is recited in the claim.
Regarding claim 11, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a signal line suspended above the memory cells and extending lengthwise along the first direction, wherein the signal line includes a first segment coupled to the pass-gate transistors of a first portion of the memory cells and a second segment coupled to the pass-gate transistors of a second portion of the memory cells, and wherein the first segment has a first width and the second segment has a second width that is smaller than the first width.” in combination with the other limitations thereof as is recited in the claim. Claims 12-17 depend on claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUAN HOANG whose telephone number is (571)272-1779. The examiner can normally be reached 7:30AM-4:00PM M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUAN HOANG/Primary Examiner, Art Unit 2827
Prosecution Insights