DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-15) and new claims 16/20 in the reply filed on 05/20/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “Method of Forming Semiconductor Package With Bonding Regions Having Differing Amounts of Inter-Metallic Compound and Solder”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakuma et al. (US 2023/0197657 A1; hereinafter, “Sakuma”) in view of Daoud et al. (US 2021/0154775 A1; hereinafter, “Daoud”).
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Regarding claim 1:
Sakuma discloses a method comprising:
forming a first conductive pillar 754 (Fig. 7, [0052] and see “first conductive pillar” in Exhibit A above) on an interposer 620 ([0046] and see “Interposer” in Exhibit A);
forming a second conductive pillar 660/662 (Fig. 8A, [0048] and see “second conductive pillar” in Exhibit A) on the interposer 620, wherein the second conductive pillar 660/662 comprises a first barrier layer 662 (Fig. 8A and [0048]);
bonding a first semiconductor device 610 (Fig. 10, [0046] and see “Semiconductor device” in Exhibit A) to the first conductive pillar (see “first conductive pillar” in Exhibit A) by a first bonding region (see “first bonding region” in Exhibit A)
bonding the first semiconductor device 610 to the second conductive pillar by a second bonding region (see “second bonding region” in Exhibit A) comprising more solder
Sakuma does not disclose a relationship between amounts of solder and intermetallic compound in each of the first and second bonding regions. However, it is noted that Sakuma discloses (in [0061]) the volume of solder layer 670 (i.e., in the first bonding region) is less than the volume of solder layer 664 (i.e., in the second bonding region).
Daoud is cited to show it was well known in the art that solder can easily transforms completely into intermetallic compounds (CuSn3 and Cu6Sn5, [0094]) when used to bond copper.
It would have been obvious to one of ordinary skill in the art to specifically bond Sakuma’s interposer and first semiconductor device such that the first bonding region (which starts with less solder) comprises more inter-metallic compound than solder and the second bonding region (which starts with more solder) comprises more solder than inter-metallic compound, because Daoud shows/teaches solder is easily transformed completely into intermetallic compound, and because Sakuma specifically incorporated more solder in the second bonding region in order to the second bonding region to be capable of compressing and/or deforming to form a solder elbow (e.g., 1010 in Fig. 10 and [0059]).
Regarding claims 2-9:
re claim 2, Sakamura discloses the first conductive pillar 754 is copper (i.e., at least “668” is copper, [0048]);
re claim 3, Sakamura discloses the first barrier layer 662 (Note: “first” must be inserted before “barrier layer” because claim 1 was amended to recited “first”) is cobalt or nickel [0048];
re claim 4, Sakamura discloses the first conductive pillar 754 is formed in Fig. 7 and the second conductive pillar is formed in Fig. 8A; accordingly, the first conductive pillar is formed before the second conductive pillar in one aspect of sequence;
re claim 5, Sakamura discloses forming the second conductive pillar 660/662 (Fig. 8A) comprises: forming a copper pillar 660 [0048]; and depositing the first barrier layer 662 on the copper pillar [0048];
re claim 6, Sakamura discloses wherein bonding the second first semiconductor device 610 (Fig. 10) to the second conductive pillar (see Exhibit A) comprises:
depositing a solder layer 664 [0048] on the second conductive pillar;
placing a third conductive pillar (see “third conductive pillar” in Exhibit A) of the first semiconductor device 610 on the solder layer 664, wherein the third conductive pillar comprises a second barrier layer 666 [0048; and
performing a reflow process [0048];
re claim 7, although Sakamura discloses bonding only one semiconductor device, it would have been obvious to one of ordinary skill in the art to bond a second device by repeating the process disclosed by Sakamura, i.e., the current claim is considered to be drawn to duplicating the process and parts, and it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8;
re claim 8, Daoud discloses solder can easily transforms completely into intermetallic compounds (CuSn3 and Cu6Sn5 [0094]) when used to bond copper; accordingly, the first bonding region (which has less solder) can easily be free of solder; and
re claim 9, Although Sakamura (in view of Daoud) does not disclose a specific range of less than 10%, this claim is deemed obvious because the general conditions of the claimed invention are disclosed in the prior art, and given the prior art one of ordinary skill in the art would have been able to find an optimum or workable range the amount of inter-metallic compound. Note it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation (MPEP 2144.05). In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Therefore, claims 2-9 are rendered obvious by Sakamura in view of Daoud.
Allowable Subject Matter
Claims 10-15 and 21-25 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 10-15 are allowed primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in independent claim 10: performing at third deposition process to form a barrier layer on the plurality of second metal pillars; depositing solder material on the plurality of first metal pillars and on the plurality of second metal pillars; and bonding a plurality of dies to the plurality of first metal pillars and to the plurality of second metal pillars; and
Claims 21-25 are allowed primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in independent claim 21: wherein the second conductive features of the semiconductor device and the interposer comprise respective first barrier layers, wherein attaching the semiconductor device to the interposer comprises: placing the second conductive features of the semiconductor device on corresponding second conductive features of the interposer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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