Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 5-6, filed 06/23/2026, with respect to the rejection(s) of claim(s) 1 under USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made combining the previous references of Takeuchi and Zhao with a new reference to Jeong et al (US 20210351011). In particular, the applicants arguments hinged around the timing of the two RF signals not being disclosed as simultaneous. Jeong et al. cures said deficiencies as stated below. Because there is a new rejection, not necessitated by amendment, this action is a non-final action.
With regards to the arguments relating to independent claim 10, no amendment nor language in claim 10 suggests that the signals are produced simultaneously. Thus, with respect to the timing of the RF signals the argument is found not persuasive. Additionally, claim 10 only recites two RF signals at two separate frequencies, of which the prior art discloses, with no mention to the exact timing of when each signal or how many of each signal is produced. If the applicant wishes to change the language of claim 10 to match that of claim 1 it is recommended to introduce some temporal language. As it stands the rejection of claim 10 stands.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al (US 20220084789) in view of Zhao et al (US 20210082667), and Jeong et al (US 20210351011).
Takeuchi et al teaches
[claim 1] wherein the established dual RF frequency CCP is formed by use of the first RF generator and a second RF generator coupled to the first electrode of the plasma processing chamber (figure 3, paragraph 0075 where elements 31a and 31c are the two RF generators coupled to the same electrode of the plasma processing chamber),
the established dual RF frequency CCP is formed by delivering a second RF signal at the first RF frequency to the first electrode and a third RF signal at a second RF frequency to the first electrode (figure 6, paragraph 0075, items 2 and 6 linked to section c, there is a second signal at the first frequency [HF] delivered at the same time as the third signal at the second frequency [element LF2]),
and the first RF frequency is greater than the second RF frequency (paragraph 0075, where the frequency of HF is greater than the frequency of LF2).
Takeuchi et al does not specifically disclose,
[claim 1] A processing method, comprising: depositing a barrier layer on a field region and sidewalls of a via of an interconnect structure, wherein depositing the barrier layer comprises establishing a single RF frequency capacitively coupled plasma (CCP) using a first radio frequency (RF) generator coupled to a first electrode of a plasma processing chamber, and the single RF frequency CCP is formed by delivering a first RF signal from the first radio frequency (RF) generator at a first RF frequency to the first electrode, and treating the barrier layer by establishing a dual RF frequency CCP in the plasma processing chamber, the first RF frequency is greater than the second RF frequency,
[the established dual RF frequency CCP is formed by] simultaneously [delivering a second RF signal at the first RF frequency to the first electrode].
However, Zhao et al does teach
[claim 1] A processing method, comprising: depositing a barrier layer on a field region and sidewalls of a via of an interconnect structure (paragraphs 0085-0087 and 0093,, figures 5A-5E, where one can see that for conformal PECVD/PEALD [deposition] of the layer a single frequency is used [f1 = 100MHz] to deposit the layer onto the interconnects, where such frequency is sent from a first RF generator by a first RF signal to the first electrode),
wherein depositing the barrier layer comprises establishing a single RF frequency capacitively coupled plasma (CCP) using a first radio frequency (RF) generator coupled to a first electrode of a plasma processing chamber (figures 1 and 2, paragraphs 0044-0046, where element 12 is the first RF generator, and element 206 is the top electrode [figure 2] where frequency f1 [first frequency] is sent to the top electrode);
and the single RF frequency CCP is formed by delivering a first RF signal from the first radio frequency (RF) generator at a first RF frequency to the first electrode (figure 1 and 2, paragraphs 0044-0046, and paragraphs 0085-0087, and 0093, where the first frequency [f1] is sent from the first RF generator [element 12 of figure 1] to the top electrode [element 206 of figure 2]),
and treating the barrier layer by establishing a dual RF frequency CCP in the plasma processing chamber (figures 5A-5E, paragraph 0093, where figure 5E shows a plurality of frequencies used and in particular frequency f3 [labeled as the ‘second frequency’ here on out] is used to treat the barrier layer),
first RF frequency is greater than the second RF frequency (figure 5E, where f1 [100 MHz] is the first frequency and is greater than f3 [second frequency at 60 Mhz]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al to incorporate the teachings of Zhao et al in order to enhance the deposition of the material onto the interconnect by using multiple frequencies, thus staying away from high temperatures and chemical byproducts.
Additionally, Takeuchi et al as modified does not specifically disclose
[claim 1] [the established dual RF frequency CCP is formed by] simultaneously [delivering a second RF signal at the first RF frequency to the first electrode].
However, Jeong et al does teach
[claim 1] [the established dual RF frequency CCP is formed by] simultaneously [delivering a second RF signal at the first RF frequency to the first electrode] (figure 3B, paragraph 0052, where frequency 1 and frequency 3 are 13.56 MHz applied simultaneously [as shown in figure 3B] to the first electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Takeuchi et al as modified to incorporate the teachings of Jeong et al in order to control plasma density to allow for more control over the plasma and its deposition of materials onto the device to maximize precision.
Regarding claims 8-9,
Takeuchi et al further discloses
[claim 8] The plasma processing system of claim 1, wherein the first frequency is greater than 13.56 MHz (paragraph 0031, where the first frequency [HF] is between 20 MHZ-60MHz [greater than 13.56 MHz]).
[claim 9] The plasma processing system of claim 1, wherein the second frequency is less than or equal to 13.56 MHz (paragraph 0033, the second frequency [LF2] is between 100kHz and 4MHz, thus below 13.56 MHz).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al (US 20220084789), Zhao et al (US 20210082667), and Jeong et al (US 20210351011) in further view of Cheng et al (US 20150076695).
Takeuchi et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 2] The method of claim 1, wherein the processing method further comprises selectively depositing a passivation layer on an exposed portion of a conductive layer formed within a via of the interconnect structure prior to depositing the barrier layer.
However, Takeuchi et al as modified above does not specifically disclose
[claim 2] The method of claim 1, wherein the processing method further comprises selectively depositing a passivation layer on an exposed portion of a conductive layer formed within a via of the interconnect structure prior to depositing the barrier layer.
However, Cheng et al does teach
[claim 2] The method of claim 1, wherein the processing method further comprises selectively depositing a passivation layer on an exposed portion of a conductive layer formed within a via of the interconnect structure prior to depositing the barrier layer (paragraph 0043, figure 7, where the passivation layer [element 120] is deposited on a conductive layer [element 108] before the deposition of a barrier layer [element 122] onto an interconnect structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al as modified with the teachings of Cheng et al in order to prevent early via voiding [paragraph 0043].
Claim(s) 3, 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al (US 20220084789), Zhao et al (US 20210082667), Jeong et al (US 20210351011), and Cheng et al (US 20150076695) and in further view of Cheng et al (US 20210217662).
Takeuchi et al as modified above teaches all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claim 3] The method of claim 2, wherein the passivation layer comprises a self-assembled monolayer (SAM).
However, Cheng et al does teach
[claim 3] The method of claim 2, wherein the passivation layer comprises a self-assembled monolayer (SAM) (paragraph 0045, where the passivation layer deposited prior to the barrier layer is a self-assembled monolayer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al as modified with the teachings of Cheng et al to use a SAM layer to effectively control the surface oxidation to keep out contaminants from the device improving efficiency of the device.
Regarding claims 5 and 6
Takeuchi et al as modified does not specifically teach,
[claim 5] The method of claim 2, wherein the conductive layer comprises copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo).
[claim 6] The method of claim 5, wherein the field region and sidewalls comprise a low-k dielectric material.
However, Cheng et al (US 20150076695) further teaches
[claim 5] The method of claim 2, wherein the conductive layer comprises copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo) (paragraph 0020, where the conductive material, element 108, can be made of copper.
[claim 6] The method of claim 5, wherein the field region and sidewalls comprise a low-k dielectric material (paragraph 0019, where the sidewalls contain a low-k dielectric material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al as modified with the teachings of Cheng et al in order to use a conductive material and a low-k dielectric material for proper conductivity and shielding to allow proper function of the device, thus improving efficiency.
Regarding claim 7,
Takeuchi et al further discloses
[claim 7] The method of claim 6, wherein the first frequency greater than 13.56 MHz and the second RF frequency that is less than13.56 MHz (paragraphs 0031 and 0033, where the first frequency [HF] is between 20 MHZ-60MHz [greater than 13.56 MHz], and the second frequency [LF2] is between 100kHz and 4MHz, thus below 13.56 MHz).
Claim(s) 10-13 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al (US 20220084789) in view of Zhao et al (US 20210082667).
Takeuchi et al teaches
[claim 10] A plasma processing system comprising: a first radio frequency (RF) generator coupled an electrode of a processing chamber of the plasma processing system (figure 2, paragraph 0074, where element 31a is the first rf generator and connected to an electrode of the plasma chamber),
the first RF generator configured to generate a first RF signal having a first frequency (paragraph 0074, where element 31a has a first frequency HF);
a second RF generator coupled the electrode of the processing chamber of the plasma processing system (paragraph 0075, figure 2, where element 31c is the second rf generator),
the second RF generator configured to generate a second RF signal having a second frequency, the second frequency and the first frequency being different (paragraph 0075, figure 2, where element 31c produces a frequency, LF2, and LF2 is different than HF);
a controller; and a memory for storing instructions, which, when executed by the controller, causes the controller to perform a processing method (paragraph 0023, figure 2, element 2 is the controller with memory for storing instructions [computer containing a storage unit, element 21b] for executing a processing method),
the method comprising: establishing, by use of the first RF generator, a single RF frequency capacitively coupled plasma (CCP), during performing a first processing operation (paragraphs 0074-0076, figure 6, where first a single RF frequency is listed as HF and sent from the first RF generator),
and establishing, by use of the first RF generator and the second RF generator, a dual RF frequency CCP during performing a second processing operation (paragraphs 0074-0076, figure 6, where in part c of the process there is the first RF frequency [HF] and the second [LF2] from the first RF generator and second RF generator respectively, at the same time to create a capacitively coupled plasma).
Takeuchi et al does not specifically disclose,
[claim 10] upper [electrode] and [a processing method] on an interconnect structure.
However, Zhao et al does teach
[claim 10] upper [electrode] and [a processing method] on an interconnect structure (figures 1 and 2, paragraphs 0044-0046, where the RF generator is connected to an upper electrode, and the purpose of the process is depositing and treatment of an interconnect structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al to incorporate the teachings of Zhao et al in order to enhance the deposition of the material onto the interconnect by using multiple frequencies, thus staying away from high temperatures and chemical byproducts.
Regarding claims 11-13,
Takeuchi et al further discloses
[claim 11] The plasma processing system of claim 10, wherein the first frequency is greater than the second frequency (paragraphs 0031 and 0033, where the first frequency [HF] is between 20 MHZ-60MHz and the second frequency [LF2] is between 100kHz and 4MHz, thus the first frequency is greater than the second frequency).
[claim 12] The plasma processing system of claim 10, wherein the first frequency is greater than 13.56 MHz (paragraph 0031, where the first frequency [HF] is between 20 MHZ-60MHz [greater than 13.56 MHz]).
[claim 13] The plasma processing system of claim 10, wherein the second frequency is less than or equal to 13.56 MHz (paragraph 0033, the second frequency [LF2] is between 100kHz and 4MHz, thus below 13.56 MHz).
Regarding claims 17 and 18,
Takeuchi et al further discloses
[claim 17] The plasma processing system of claim 10, wherein the first RF generator and the second RF generator are coupled to an RF matching network that is coupled to the electrode of the processing chamber (abstract, paragraphs 0031-0032, where the first and second RF generators [elements 31a and 31c respectively] have matching circuits elements 33 and 34 respectively).
[claim 18] The plasma processing system of claim 17, wherein the RF matching network comprises a first RF match coupled to the first RF generator and a second RF match coupled to the second RF generator (abstract, paragraphs 0031-0032, where the first and second RF generators [elements 31a and 31c respectively] have matching circuits elements 33 and 34 respectively).
However, Takeuchi et al does not specifically disclose
[claim 17] [coupled to the] upper [electrode]
However, Zhao et al does teach
[claim 17] [coupled to the] upper [electrode] (figures 1 and 2, paragraphs 0044-0046, where the RF generator is connected to an upper electrode).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al as modified to incorporate the teachings of Zhao et al to enhance the deposition of the material onto the interconnect by using multiple frequencies attached to an upper electrode, thus staying away from high temperatures and chemical byproducts.
Claim(s) 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al (US 20220084789), Zhao et al (US 20210082667), and Jeong et al (US 20210351011) in further view of Cheng et al (US 20150076695).
Takeuchi et al further discloses
[claim 16] The plasma processing system of claim 10, wherein the controller is configured to enable the first RF generator and the second RF generator and establish a dual RF frequency capacitively coupled plasma (CCP) in the processing chamber when treating a layer (paragraphs 0077-0079, figure 6, where part C of the process establishes a dual RF frequency capacitively coupled plasma in the process chamber that treats a layer).
Takeuchi et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 14] The plasma processing system of claim 10, wherein the controller is configured to enable the first RF generator and establish a single RF frequency capacitively coupled plasma (CCP) in the processing chamber when removing a passivation layer formed in a via of an interconnect structure.
[claim 16] [when treating a] barrier layer formed on a field region and on sidewalls of a via of an interconnect structure.
However, Zhao et al does teach
[claim 14] The plasma processing system of claim 10, wherein the controller is configured to enable the first RF generator and establish a single RF frequency capacitively coupled plasma (CCP) in the processing chamber when removing a layer formed in a via of an interconnect structure (figure 5B – 5E, paragraphs 0087-0089 and 0093, where element 513 is a layer removed by a single frequency [f2] in a capacitively coupled plasma chamber when removing the layer on an interconnect [510]).
[claim 16] [when treating a] layer formed on a field region and on sidewalls of a via of an interconnect structure (figure 5B – 5E, paragraphs 0087-0089 and 0093, where element 513 and 518 are treated on an interconnect structure by a dual RF capacitively coupled plasma chamber).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al as modified to incorporate the teachings of Zhao et al to remove a layer before depositing another layer, and the controller configured to do so, in order to deposit a barrier layer on a clean surface to minimize defects and improve overall efficiency of the device.
However, Takeuchi et al as modified above does not specifically disclose
[claim 14] [when removing a] passivation [layer]
[claim 16] barrier [layer]
However, Cheng et al does teach
[claim 14] [when removing a] passivation [layer] (paragraph 0043, where a passivation layer is removed before deposition of barrier layer).
[claim 16] barrier [layer] (paragraph 0038, figure 5, where the barrier layer is deposited on the interconnect structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al as modified with the teachings of Cheng et al in order to prevent early via voiding [paragraph 0043].
Claim(s) 15 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al (US 20220084789), Zhao et al (US 20210082667) and Cheng et al (US 20150076695) and in further view of Cheng et al (US 20210217662).
Regarding claim 15, Takeuchi et al further discloses
the first frequency is greater than 13.56 MHz, and the second frequency is less than or equal to 13.56 MHz (paragraphs 0031 and 0033, where the first frequency [HF] is between 20 MHZ-60MHz and the second frequency [LF2] is between 100kHz and 4MHz, thus the first frequency is greater than the second frequency).
However, Takeuchi et al as modified above teaches all of the limitations of the parent claim, claim 14, but does not specifically disclose
[claim 15] The plasma processing system of claim 14, wherein the passivation layer comprises a self-assembled monolayer (SAM)
However, Cheng et al does teach
[claim 15] The plasma processing system of claim 14, wherein the passivation layer comprises a self-assembled monolayer (SAM) (paragraph 0045, where the passivation layer deposited prior to the barrier layer is a self-assembled monolayer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al as modified with the teachings of Cheng et al to use a SAM layer to effectively control the surface oxidation to keep out contaminants from the device improving efficiency of the device.
Claim(s) 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi et al (US 20220084789), and Zhao et al (US 20210082667) in further view of Cui et al (US 20220399193).
Takeuchi et al as modified teaches all of the limitations of the parent claim, claim 10, but does not specifically disclose
[claim 19] The plasma processing system of claim 10, wherein the processing chamber further comprises a substrate support assembly comprising biasing electrode coupled to a clamping network and a grounded substrate support base.
[claim 20] The plasma processing system of claim 19, wherein the clamping network comprises bias compensation circuit elements coupled to a DC power supply.
However, Cui et al does teach
[claim 19] The plasma processing system of claim 10, wherein the processing chamber further comprises a substrate support assembly comprising biasing electrode coupled to a clamping network and a grounded substrate support base (paragraphs 0049-0050, figure 1A, where the substrate support assembly [element 136] contains a biasing electrode [element 104] and a clamping network [element 116], and a support base [element 123] which is grounded [as seen in the image]).
[claim 20] The plasma processing system of claim 19, wherein the clamping network comprises bias compensation circuit elements coupled to a DC power supply (paragraphs 0049-0050, figure 1A, where the DC power supply [element 155] is coupled to a circuit coupled to the clamping network [element 116]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have modified the teachings of Takeuchi et al as modified to incorporate the teachings of Cui et al in order to ground and bias the plasma such that no arc or electrostatic shock may happen to or within the chamber thus affecting the quality of the device during creation with the plasma chamber.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights