CTNF 18/434,215 CTNF 80387 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-08 AIA Restriction to one of the following inventions is required under 35 U.S.C. 121: I. Claim s 16-24 and 31-35 , drawn to a method of manufacturing a transistor that forms a dielectric structure around a top corner of a gate structure to replace a portion of an interlayer dielectric structure that has been removed during manufacture , classified in H10D 64/011 . II. Claim s 25-30 , drawn to a method of manufacturing a transistor that removes a portion dielectric layer deposited over an interlayer dielectric structure and replaces the portion of the dielectric layer with another dielectric material , classified in H10W 20/47 . 08-13 AIA The inventions are independent or distinct, each from the other because: 08-14-01 AIA Inventions I and II are directed to related processes . The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed are not capable of use together, do not overlap in scope, and are not obvious variants because the method of manufacturing a transistor that forms a dielectric structure around a top corner of a gate structure to replace a portion of an interlayer dielectric structure that has been removed during manufacture and the method of manufacturing a structure that has a first transistor existing in two other transistors and a second transistor existing in two other transistors manufacture transistors using different manufacturing steps. In particular, the method of a method of manufacturing a transistor that forms a dielectric structure around a top corner of a gate structure to replace a portion of an interlayer dielectric structure that has been removed during manufacture recites etching the ILD structure to form a source/drain contact opening exposing one of the source/drain epitaxial structures, wherein a top corner of the gate structure is exposed through the source/drain contact opening, while, the method of manufacturing transistor that removes a portion dielectric layer deposited over an interlayer dielectric structure and replaces the portion of the dielectric layer with another dielectric material recites performing an etching process to the dielectric layer to expose one of the source/drain epitaxial structures, wherein a portion of the gate structure exposed thought the source/drain contact opening as a result of the etching process . Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants. Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply: inventions have acquired a separate status in the art in view of their different classification, and the inventions require a different field of search (e.g. searching different class/subclasses or electronic resources, or employing different search strategies or search queries). The examiner now points out that applicant elected claims 16-20 in the response filed on May 22, 2026 and that claims 25-30 are directed to invention II which is independent or distinct from invention I, the invention elected by the applicant. Therefore, invention I directed toward claims 16-24 and 31-35 has been constructively elected by original presentation for prosecution on the merits and invention II directed toward claims 25-30 is withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03. To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention 08-23-02 AIA Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i). Drawings 06-22-06 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: reference number 120B for right dummy gate structure referred to in paragraphs 11, 13-14, 16, and 18 is not shown in figure 1 . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters “180A and 180B” have been used to designate different dielectric liners shown in figures 7-8 and 12-13 and reference character “184” has been used to designate different dielectric layers in figures 6-8 and 11-13. The examiner notes that the dielectric liner shown in figures 7-8 is structurally different from the dielectric liner shown in figures 12-13, and thus, the dielectric liner shown in figures 7-8 is a different part from the dielectric liner shown in figures 11-13. The examiner also notes the dielectric layer shown in figures 7-8 is structurally different from the dielectric layer shown in figures 11-13 because the dielectric layers have different surfaces, in particular, the dielectric layer shown in 11-13 has surface that has been oxidized and has Si-O bonds at the surface replaced with Si-F bonds. See paragraph 51-53. Thus, the dielectric layer shown in figures 7-8 is a different part from the dielectric layer shown in figures 11-13. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 07-30-02 AIA 12. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 13. Claims 16-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. 14. Claim 16 recites the limitation “source/drain epitaxial structures over the substrate and on opposite sides of the gate structure,” on page 2 lines 9-10. The examiner first notes that “A process defines ‘actions’, i.e., an invention that is claimed as an act or step, or a series of acts or steps.” See MPEP 2106.03 Section I. The examiner next notes that this limitation renders the claim indefinite because is it unclear what steps or acts are required by this limitation. For examination purposes, this limitation will be interpreted as forming source/drain epitaxial structures over the substrate and on opposite sides of the gate structure. Claims 17-24 are also rejected for containing the same limitation because claims 17-24 depend from claim 16. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 16-17, 19-24, and 31-35 are rejected under 35 U.S.C. 103 as being unpatentable over Kuroda (US 5,825,059) in view of Wang et al. (US 2013/0178029) further in view of Doyle et al. (US 2020/0388711) . Regarding Claim 16: Kuroda discloses a method, comprising: forming a gate structure (forming a gate electrode, See fig. 2A, ref. nos. 12-15 and col. 4 lines 47-64. The examiner notes that figure 2A shows two gate electrodes and the right gate electrode is being read on a gate structure.) over a substrate (semiconducting substrate, See fig. 2a, ref. no. 10 and col. 4 lines 47-64); source/drain structures (forming diffusion layers as source/drain regions to the left and the right of the right gate electrode, See fig. 2A, ref. no. 17, col. 3 lines 25-30 and col. 4 lines 47-64) over the substrate and on opposite sides of the gate structure; forming an interlayer dielectric (ILD) structure (forming a interlayer insulating film on the semiconducting substrate, See fig. 2B, ref. no. 18, col. 4 lines 66-67 and col. 5 lines 1-10) laterally surrounding and covering the gate structure; etching the ILD structure to form a source/drain contact opening (reactive ion etching the interlayer insulating film to form an opening exposing the right diffusion layer, See fig. 2B, ref. no. 19, col. 4 lines 66-67 and col. 5 lines 1-10) exposing one of the source/drain structures, wherein a top corner of the gate structure is exposed through the source/drain contact opening (the top right corner of right gate electrode is exposed through the opening, See fig. 2B, ref. nos. 15, 19); depositing a dielectric layer lining (depositing an insulating film lining the opening, See fig. 3A, ref. nos. 19, 20 and col. 5 12-23) the source/drain contact opening; and forming a source/drain contact (forming a contact plug in the opening, See fig. 4B, ref. no. 22 and col. 6 lines 18-31) in the source/drain contact opening. Kuroda does not disclose the source/drain structures are source/drain epitaxial structures and selective depositing a dielectric material wraps the top corner of the gate structure. Wang discloses selective epitaxial growth of source/drain features in cavities on both sides of a gate structure (See fig. 9, ref. nos. 220, 230 and paragraph 27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of making a semiconductor device of Kuroda to selectively grow source/drain features in cavities on both side of a gate structure as taught as by Wang in order to enhance semiconductor device performance by improving carrier mobility. (See Wang paragraph 13.) The above stated combination of Kuroda and Wang does not disclose selective depositing the dielectric material wraps the top corner of the gate structure. Doyle discloses selectively depositing gate dielectric material onto an exposed sidewall of a gate electrode (See fig. 1, ref. no. 140 and paragraphs 32-33). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of making a semiconductor device of Kuroda and Wang to include selectively depositing dielectric material on the exposed portion of the polycrystalline silicon layer and the silicide layer of the gate electrode as taught by Doyle in order to reduce the space of the opening occupied by the insulating film by only forming a double layer structure over the exposed portion of the gate electrode. Regarding Claim 17: The combination Kuroda, Wang, and Doyle discloses wherein selective depositing the dielectric material is performed prior to depositing the dielectric layer (the examiner notes that Doyle discloses selectively depositing gate dielectric material onto an exposed sidewall of a gate electrode, thus, the gate dielectric material of Doyle is deposited before the insulating layer of Kuroda, See Doyle fig. 1, ref. no. 140 and paragraph 32-33). Regarding Claim 19: Kuroda discloses wherein the dielectric layer is in contact with the ILD structure (the insulating film is in contact with interlayer insulating film, See fig. 3A, ref. nos. 18, 20, and col. 5 lines 12-24). Regarding Claim 20: Kuroda discloses etching the dielectric layer to expose the one of the source/drain epitaxial structures prior to forming the source/drain contact (anisotropically etching the insulating film on the bottom portion of the opening, See fig. 4A and col. 5 lines 50-67). Regarding Claim 21: The combination Kuroda, Wang, and Doyle discloses wherein the dielectric material and the dielectric layer comprise different compositions (Doyle discloses depositing metal oxides and Kuroda discloses depositing dielectrics containing silicon, such as silicon nitride, See Doyle paragraph 32-33 and Kuroda col. 5 lines 12-24). Regarding Claim 22: The combination Kuroda, Wang, and Doyle discloses wherein the dielectric material has a higher oxygen atomic concentration than the dielectric layer (Doyle discloses depositing metal oxides, which contain oxygen and Kuroda discloses depositing silicon nitride, which does not contain oxygen, See Doyle paragraph 32-33 and Kuroda col. 5 lines 12-24). Regarding Claim 23: The combination of Kuroda, Wang, and Doyle discloses wherein the dielectric material has a lower silicon atomic concentration than the dielectric layer (Doyle discloses depositing metal oxides, which do not contain silicon and Kuroda discloses depositing silicon nitride, which contains silicon, See Doyle paragraph 32-33 and Kuroda col. 5 lines 12-24) Regarding Claim 24: The combination of Kuroda, Wang, and Doyle discloses wherein the dielectric material has a lower nitrogen atomic concentration than the dielectric layer (Doyle discloses depositing metal oxides, which do not contain nitrogen and Kuroda discloses depositing silicon nitride, which contains nitrogen, See Doyle paragraph 32-33 and Kuroda col. 5 lines 12-24). Regarding Claim 31: Kuroda discloses a method, comprising: forming a gate structure (forming a gate electrode, See fig. 2A, ref. nos. 12-15 and col. 4 lines 47-64. The examiner notes that figure 2A shows two gate electrodes and the right gate electrode is being read on a gate structure.) over a substrate (semiconducting substrate, See fig. 2a, ref. no. 10 and col. 4 lines 47-64); forming source/drain structures (forming diffusion layers as source/drain regions to the left and the right of the right gate electrode, See fig. 2A, ref. no. 17, col. 3 lines 25-30 and col. 4 lines 47-64) on opposite sides of the gate structure; forming an interlayer dielectric (ILD) structure (forming a interlayer insulating film on the semiconducting substrate, See fig. 2B, ref. no. 18, col. 4 lines 66-67 and col. 5 lines 1-10) surrounding and covering the gate structure; forming a dielectric liner lining a sidewall of the ILD structure (reactive ion etching the interlayer insulating film to form an opening exposing the right diffusion layer and depositing an insulating film lining the opening, See fig. 2B, ref. no. 19, fig. 3A, ref. nos. 19, 20, col. 4 lines 66-67 and col. 5 lines 1-23) and wrapping a top corner of the gate structure (the insulating film covers the top right corner of the right gate electrode, See fig. 3A, ref. nos. 15 and 20), wherein the dielectric liner comprises: a bottom portion (portion of the insulating film covering the gate oxide film, See fig. 3A, ref. nos. 12 and 20); a top portion above the bottom portion (portion of the insulating film covering the interlayer insulating film above the gate electrode, See fig. 3A, ref. nos. 15, 18, and 20); and a middle portion (portion of the insulating film covering the polycrystalline silicon layer and the silicide layer of the gate electrode, See fig. 2A, ref. nos. 13, 14, fig. 3A, ref. nos. 15, 20, and col. 4 lines 47-64) connecting the bottom portion and the top portion. Kuroda disclose the source/drain structures are source/drain epitaxial structures and wherein the middle portion has a different composition than the bottom portion and the top portion. Wang discloses selective epitaxial growth of source/drain features in cavities on both sides of a gate structure (See fig. 9, ref. nos. 220, 230 and paragraph 27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of making a semiconductor device of Kuroda to selectively grow source/drain features in cavities on both side of a gate structure as taught as by Wang in order to enhance semiconductor device performance by improving carrier mobility. (See Wang paragraph 13.) The above stated combination of Kuroda and Wang does not disclose wherein the middle portion has a different composition than the bottom portion and the top portion. Doyle discloses selectively depositing gate dielectric material onto an exposed sidewall of a gate electrode (See fig. 1, ref. no. 140 and paragraphs 32-33). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of making a semiconductor device of Kuroda and Wang to include selectively depositing dielectric material on the exposed portion of the polycrystalline silicon layer and the silicide layer of the gate electrode as taught by Doyle in order to reduce the space of the opening occupied by the insulating film by only forming a double layer structure over the exposed portion of the gate electrode. (The examiner notes that middle portion of the dielectric liner formed by the combination of Kuroda, Wang, and Doyle will have a different composition than the bottom portion and the top portion because the middle portion has a double layer structure formed by two layers of different dielectric material.) Regarding Claim 32: Kuroda discloses wherein the bottom portion and the top portion have a same composition (the insulating film has the same composition, See fig. 3A, ref. no. 20 and col. 5 lines 12-24). Regarding Claim 33: The combination of Kuroda, Wang, and Doyle discloses wherein the bottom portion, the top portion, and the middle portion comprise silicon nitride, and the middle portion has a higher oxygen atomic concentration than the bottom portion and the top portion (the bottom portion and the top portion are formed from silicon nitride and the middle portion has a double layer structure formed by silicon nitride and a metal oxide, See Kuroda col. 5 lines 12-24 and Doyle paragraphs 32-33). Regarding Claim 34: The combination of Kuroda, Wang, and Doyle disclose wherein the middle portion is in contact with the top corner of the gate structure (the double layer structure formed by silicon nitride and a metal oxide, See Kuroda fig. 3A, ref. nos. 13, 14, 20, col. 5 lines 12-24, and Doyle paragraphs 32-33). Regarding Claim 35: Kuroda discloses wherein the bottom portion and the top portion are spaced apart from the top corner of the gate structure (portion of the insulating film covering the gate oxide film and the portion of the insulating film covering the interlayer insulating film above the gate electrode are space apart from the double layer structure covering the polycrystalline silicon layer and the silicide layer, See fig. 3A, ref. nos. 15 and 20) . 07-21-aia AIA Claim s 16 and 18-24 are rejected under 35 U.S.C. 103 as being unpatentable over Kuroda (US 5,825,059) in view of Wang et al. (US 2013/0178029) further in view of Ichihara et al. (US 2006/0180870) . Regarding Claim 16: Kuroda discloses a method, comprising: forming a gate structure (forming a gate electrode, See fig. 2A, ref. nos. 12-15 and col. 4 lines 47-64. The examiner notes that figure 2A shows two gate electrodes and the right gate electrode is being read on a gate structure.) over a substrate (semiconducting substrate, See fig. 2a, ref. no. 10 and col. 4 lines 47-64); source/drain structures (forming diffusion layers as source/drain regions to the left and the right of the right gate electrode, See fig. 2A, ref. no. 17, col. 3 lines 25-30 and col. 4 lines 47-64) over the substrate and on opposite sides of the gate structure; forming an interlayer dielectric (ILD) structure (forming a interlayer insulating film on the semiconducting substrate, See fig. 2B, ref. no. 18, col. 4 lines 66-67 and col. 5 lines 1-10) laterally surrounding and covering the gate structure; etching the ILD structure to form a source/drain contact opening (reactive ion etching the interlayer insulating film to form an opening exposing the right diffusion layer, See fig. 2B, ref. no. 19, col. 4 lines 66-67 and col. 5 lines 1-10) exposing one of the source/drain structures, wherein a top corner of the gate structure is exposed through the source/drain contact opening (the top right corner of right gate electrode is exposed through the opening, See fig. 2B, ref. nos. 15, 19); depositing a dielectric layer lining (depositing an insulating film lining the opening, See fig. 3A, ref. nos. 19, 20 and col. 5 12-23) the source/drain contact opening; and forming a source/drain contact (forming a contact plug in the opening, See fig. 4B, ref. no. 22 and col. 6 lines 18-31) in the source/drain contact opening. Kuroda does not disclose the source/drain structures are source/drain epitaxial structures and selective depositing a dielectric material wraps the top corner of the gate structure. Wang discloses selective epitaxial growth of source/drain features in cavities on both sides of a gate structure (See fig. 9, ref. nos. 220, 230 and paragraph 27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify method of making a semiconductor device of Kuroda to selectively grow source/drain features in cavities on both side of a gate structure as taught as by Wang in order to enhance semiconductor device performance by improving carrier mobility. (See Wang paragraph 13.) The above stated combination of Kuroda and Wang does not disclose selective depositing the dielectric material wraps the top corner of the gate structure. Ichihara discloses selectively depositing a gate dielectric on a previously deposited gate dielectric (See fig. 11, ref. nos. 9, 10, and paragraph 73). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of making a semiconductor device of Kuroda and Wang to include selectively depositing dielectric material on the dielectric layer lining the source/drain contact opening as taught by Ichihara in order to forming a double layer structure over the exposed portion of the gate electrode with a reduced the amount of material that must be subsequently removed from the surface of the interlayer insulating film. Regarding Claim 18: The combination of Kuroda, Wang, and Ichihara discloses wherein selective depositing the dielectric material is performed after depositing the dielectric layer (See Ichihara fig. 11, ref. nos. 9, 10, and paragraph 73). Regarding Claim 19: Kuroda discloses wherein the dielectric layer is in contact with the ILD structure (the insulating film is in contact with interlayer insulating film, See fig. 3A, ref. nos. 18, 20, and col. 5 lines 12-24). Regarding Claim 20: Kuroda discloses etching the dielectric layer to expose the one of the source/drain epitaxial structures prior to forming the source/drain contact (anisotropically etching the insulating film on the bottom portion of the opening, See fig. 4A and col. 5 lines 50-67). Regarding Claim 21: The combination Kuroda, Wang, and Ichihara discloses wherein the dielectric material and the dielectric layer comprise different compositions (Ichihara discloses the selectively deposited gate dielectric is different from the previously deposited gate dielectric, See Ichihara paragraph 38). Regarding Claim 22: The combination Kuroda, Wang, and Ichihara discloses wherein the dielectric material has a higher oxygen atomic concentration than the dielectric layer (Ichihara discloses depositing aluminum oxide, which contains oxygen and Kuroda discloses depositing silicon nitride, which does not contain oxygen, See Ichihara paragraph 38 and Kuroda col. 5 lines 12-24). Regarding Claim 23: The combination of Kuroda, Wang, and Ichihara discloses wherein the dielectric material has a lower silicon atomic concentration than the dielectric layer (Ichihara discloses depositing aluminum oxide, which does not contain silicon and Kuroda discloses depositing silicon nitride, which contains silicon, See Ichihara paragraph 38 and Kuroda col. 5 lines 12-24) Regarding Claim 24: The combination of Kuroda, Wang, and Ichihara discloses wherein the dielectric material has a lower nitrogen atomic concentration than the dielectric layer (Ichihara discloses depositing aluminum oxide, which does not contain nitrogen and Kuroda discloses depositing silicon nitride, which contains nitrogen, See Ichihara paragraph 38 and Kuroda col. 5 lines 12-24). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRETT SQUIRES whose telephone number is (571)272-8214. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899 /B.S./Examiner, Art Unit 2899 Application/Control Number: 18/434,215 Page 2 Art Unit: 2899 Application/Control Number: 18/434,215 Page 3 Art Unit: 2899 Application/Control Number: 18/434,215 Page 4 Art Unit: 2899 Application/Control Number: 18/434,215 Page 5 Art Unit: 2899 Application/Control Number: 18/434,215 Page 6 Art Unit: 2899 Application/Control Number: 18/434,215 Page 7 Art Unit: 2899 Application/Control Number: 18/434,215 Page 8 Art Unit: 2899 Application/Control Number: 18/434,215 Page 9 Art Unit: 2899 Application/Control Number: 18/434,215 Page 10 Art Unit: 2899 Application/Control Number: 18/434,215 Page 11 Art Unit: 2899 Application/Control Number: 18/434,215 Page 12 Art Unit: 2899 Application/Control Number: 18/434,215 Page 13 Art Unit: 2899 Application/Control Number: 18/434,215 Page 14 Art Unit: 2899 Application/Control Number: 18/434,215 Page 15 Art Unit: 2899 Application/Control Number: 18/434,215 Page 16 Art Unit: 2899 Application/Control Number: 18/434,215 Page 17 Art Unit: 2899 Application/Control Number: 18/434,215 Page 18 Art Unit: 2899
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