DETAILED ACTION
Election/Restrictions
Applicants’ election with traverse of Species I in the reply filed on 06/01/2026 is acknowledged. Furthermore, the arguments regarding claims 18 and 32 on page 9 are persuasive and so the claims will be examined in this office action.
The pending claims in the instant application are claims 15-34.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/06/2024, 08/22/2024, 02/17/2025 and 09/25/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites: “the method of claim 21, wherein the planar top surface of the first passivation layer, after planarizing, has a degree of planarity in a range of 0 kÅ to 50kÅ.”
The specification gives much smaller thicknesses for the same and nearby films:
[0017] The passivation layer 114 may be formed to a large thickness, such as a thickness in the range of 2 kÅ to 10 kÅ.
[0020] The passivation layer 118 may be formed to a large thickness, such as a thickness in the range of 2 kÅ to 10 kÅ.
[0026] The passivation layer 132 may be formed to a large initial thickness, such as a thickness in the range of 1.5 kÅ to 100 kÅ ... As a result of planarization, the top surface of the passivation layer 132 may have a high degree of planarity, such as a degree of planarity in the range of 0 kÅ to 50 kÅ.
The specification describes a range of 2 kÅ to 10 kÅ as a “large thickness” while describing the thickness of a passivation layer. In claim 22, the upper end of the range (50 kÅ) after planarization of the passivation layer, labeled as layer 132 in the specification, is therefore as large as several of those entire films stacked, and five times the maximum leftover thickness on the redistribution line. The range is so broad that it spans from a perfectly flat surface to topography equal to the full thickness of the other passivation layers. Furthermore, the specification does not disclose what quantity is being measured (peak-to-valley step height, RMS roughness, total thickness variation, or something else) nor over what lateral distance or field the measurement is taken (over a single RDL, across the gap between the two RDL’s, or over the die). Therefore, given the broad range of planarity required by claim 22, a person of ordinary skill in the art cannot determine the metes and bounds of the limitation with reasonable certainty (See Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898, 910, 110 USPQ2d 1688, 1693 (2014); MPEP § 2173.02(I)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-17, 21-24 and 26-31 are rejected under 35 U.S.C. 103 as being unpatentable over MERCHANT et al. (US 20040061177 A1), hereinafter “Merchant,” in view of WU (US 20220216141 A1), hereinafter “Wu.”
Re: Independent Claim 15, Merchant discloses a method comprising (¶0001: method of making an IC):
depositing a passivation layer over a redistribution line (Fig. 1: dielectric stack 16, i.e., passivation layer 132 of instant application, is over conductive via/runner 20/18, i.e., RDL 124 of instant application; ¶0017: dielectric stack 16 composed of low dielectric constant material), the redistribution line extending along a semiconductor substrate (Fig. 1: via 20 has a conductive runner 18 which extends along semiconductor substrate);
planarizing the passivation layer (¶0023: dielectric stack 16 is subjected to a chemical/mechanical polishing step to planarize the top surface 23), ... (a)
forming a passive device over the passivation layer (Fig. 5: passive device 14 is formed on a planar surface of dielectric stack 16, i.e., passivation layer);
depositing a dielectric layer over the passive device and the passivation layer (See Figs. 5 and 6; Fig. 6: dielectric stack 24 is deposited over device 14 and dielectric stack 16); and
forming a die connector through the dielectric layer and (See Figs. 5 and 6; Fig. 6: conductive via/runner 40/42, i.e., die connector, extends through the dielectric stack 24) ... (b), the die connector physically and electrically coupled to the passive device and to the redistribution line (Fig. 6: conductive via/runner 40/42 is physically and electrically coupled to passive device 14 and to electrically conductive via/runner 20/18).
However, Merchant does not specifically disclose wherein
(a) ... a portion of the passivation layer remaining over the redistribution line after the passivation layer is planarized;
(b) ... the portion of the passivation layer
In a similar field of endeavor, Wu discloses wherein
(a) ... a portion of the passivation layer remaining over the redistribution line after the passivation layer is planarized (Fig. 7A shows a buffer structure 204 with a top layer 218 over conductive line 110B, i.e., redistribution line; ¶0024: a planarization operation, such as CMP may be performed to planarize the upper surfaces including layer 218);
and wherein the die connector extends through
(b) ... and the portion of the passivation layer (Fig. 11 shows a conductive via 322B, i.e., die connector, extending through a first portion of buffer structure 204, i.e., passivation layer, and makes contact with conductive line 110B)
Merchant already planarizes the interconnect so a capacitor can be formed on a flat surface and later contacted by vias. Merchant’s CMP, however, stops when the copper is exposed. Wu deposits passivation over metal, planarizes that passivation by CMP or grinding, and leaves a remaining portion covering the metal, then etches vias through that remaining film to the underlying lines. Wu does so to protect the metal, provide a planar base for later processing, and still allow contact through the leftover passivation.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to modify Merchant’s planarization to use Wu’s CMP endpoint—that is, to planarize the covering dielectric and stop while a remaining portion still covers the conductive lines. Wu teaches leaving that remaining dielectric in place to protect the underlying metal and to provide a planar surface for later processing, while still allowing vias through the remaining film to the underlying lines. Applying that teaching to Merchant would form Merchant’s capacitor and vias on a protected, planar surface without exposing the metal during polish (See Wu, ¶0025).
Re: Claim 16, the combination of Merchant and Wu discloses the method of claim 15.
Wu further discloses wherein the portion of the passivation layer remaining over the redistribution line has a thickness in a range of 2 kÅ to 10 kÅ (¶0030: buffer structure 204 has a total thickness between about 4500 Å and about 6400 Å, such as 5500 Å).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to modify the method/structure of Merchant to include a buffer structure over redistribution lines as disclosed by Wu. One would be motivated to do so to provide sufficient protection to the underlying metallization layers in case one or more protrusions build up on the surfaces of the conductive lines during subsequent operations (See Wu, ¶0025).
Re: Claim 17, the combination of Merchant and Wu discloses the method of claim 15.
Merchant further discloses wherein forming the passive device comprises:
forming a first metal layer over the passivation layer, a first pattern of the first metal layer defining a first metal plate (Fig. 2: bottom plate 30, i.e., first metal layer);
depositing an insulating layer over the first metal layer (Fig. 3: dielectric layer 32, i.e., insulating layer); and
forming a second metal layer over the insulating layer, a second pattern of the second metal layer defining a second metal plate (Fig. 3: top plate 34, i.e., second metal layer, over insulating layer 32).
Re: Independent Claim 21, Merchant discloses a method comprising (¶0001: method of making an IC):
depositing a first passivation layer on a first redistribution line and a second redistribution line (Fig. 1: dielectric stack 16, i.e., passivation layer 132 of instant application, is over conductive via/runner 20/18, i.e., RDL 124 of instant application; ¶0017: dielectric stack 16 composed of low dielectric constant material), the first redistribution line extending along a semiconductor substrate (Fig. 1: via 20 has a conductive runner 18 which extends along semiconductor substrate), the second redistribution line extending along the semiconductor substrate (Fig. 1: via 22 has a conductive runner 19 which extends along semiconductor substrate), the first passivation layer filling an entirety of an area between the first redistribution line and the second redistribution line in a cross-sectional view (Fig. 1: dielectric stack 16 fills the entire area between vias 20 and 22);
planarizing the first passivation layer to have a planar top surface (¶0023: dielectric stack 16 is subjected to a chemical/mechanical polishing step to planarize the top surface 23), wherein the planar top surface of the first passivation layer extends continuously over ... (a), and the area between the first redistribution line and the second redistribution line in the cross-sectional view (Fig. 1: planar top surface 23 of dielectric stack 16 extends over area between vias 20 and 22);
forming a passive device on the planar top surface of the first passivation layer (Fig. 5: passive device 14 is formed on a planar surface of dielectric stack 16, i.e., passivation layer), the passive device vertically overlapping the area between the first redistribution line and the second redistribution line in the cross-sectional view (Fig. 1: passive device 14 overlaps area between vias 20 and 22); and
depositing a dielectric layer over the passive device and the first passivation layer.
However, Merchant does not specifically disclose wherein the passivation layer is over
(a)... the first redistribution line, the second redistribution line, ...
In a similar field of endeavor, Wu discloses wherein the passivation layer is over
(a)... the first redistribution line, the second redistribution line (Fig. 7A shows a buffer structure 204 over conductive lines 110A/110B, i.e., first and second redistribution lines), ...
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to modify Merchant to use Wu’s CMP endpoint. Merchant planarizes the interconnect until the conductive lines are exposed. Wu instead deposits a covering dielectric over the metal, planarizes that dielectric, and stops while a remaining portion still covers the conductive lines. Wu teaches doing so to protect the underlying metal and provide a planar surface for subsequent processing, while still permitting later vias through the remaining dielectric to the underlying lines. Applying that endpoint to Merchant would allow Merchant’s capacitor and vias to be formed on a protected, planar surface without exposing the metal during polish. The same vias Merchant already uses to contact the capacitor plates would then extend through the remaining passivation to the underlying lines, as Wu teaches.
Furthermore, Wu discloses a buffer structure over the metallization that is configured to protect the underlying lines if protrusions form on the conductive-line surfaces during later operations (See Wu, ¶0025). That teaching further supports leaving a covering dielectric over Merchant’s lines rather than exposing them at the CMP endpoint.
Re: Claim 22, the combination of Merchant and Wu discloses the method of claim 21.
Merchant further discloses wherein the planar top surface of the first passivation layer, after planarizing, has a degree of planarity in a range of 0 kÅ to 50kÅ (Note: given the broad range discussed in the 35 U.S.C. 112(b) rejection above, the claim is interpreted as a surface which has been planarized; Fig. 1: dielectric stack 16, i.e., first passivation layer 132 in the instant application; ¶0023: dielectric stack 16 is subjected to a chemical/mechanical polishing step to planarize the top surface 23).
Re: Claim 23, the combination of Merchant and Wu discloses the method of claim 21.
Merchant further discloses wherein planarizing the first passivation layer comprises performing a chemical mechanical polish on the first passivation layer (¶0023: dielectric stack 16 subjected to CMP).
Re: Claim 24, the combination of Merchant and Wu discloses the method of claim 21.
Wu further discloses wherein after planarizing the first passivation layer, the first passivation layer covers a top surface of the first redistribution line and a top surface of the second redistribution line (Fig. 7A shows a buffer structure 204 with a top layer 218 over conductive lines 110B and 110A, i.e., first and second redistribution lines; ¶0024: a planarization operation, such as CMP may be performed to planarize the upper surfaces including layer 218).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to modify the method/structure of Merchant to include a buffer structure over redistribution lines as disclosed by Wu. One would be motivated to do so to provide sufficient protection to the underlying metallization layers in case one or more protrusions build up on the surfaces of the conductive lines during subsequent operations (See Wu, ¶0025).
Re: Claim 26, the combination of Merchant and Wu discloses the method of claim 21.
Merchant also discloses further comprising:
forming an etch stop layer on the planar top surface of the first passivation layer prior to forming the passive device (Fig. 2: barrier layer 28, i.e., etch-stop layer; ¶0022: barrier layer 28 serves as an etch stop layer), wherein the passive device physically contacts a top surface of the etch stop layer (Fig. 6: capacitor 14, i.e., passive device on layer 28).
Re: Claim 27, the combination of Merchant and Wu discloses the method of claim 21.
Wu also discloses further comprising:
forming a die connector through the dielectric layer and through the first passivation layer (Fig. 11 shows a conductive via 322B, i.e., die connector, extending through a dielectric layer 306 a portion of buffer structure 204, i.e., passivation layer, and makes contact with conductive line 110B), the die connector being physically and electrically coupled to the first redistribution line and to a terminal of the passive device (Fig. 11 shows a conductive via 322B physically and electrically coupled to conductive line 110B and a terminal of the capacitor structure 303, i.e., passive device).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to modify the method/structure of Merchant to include a buffer structure over redistribution lines as disclosed by Wu. One would be motivated to do so to provide sufficient protection to the underlying metallization layers in case one or more protrusions build up on the surfaces of the conductive lines during subsequent operations (See Wu, ¶0025).
Re: Independent Claim 28, Merchant discloses a method (¶0001: method of making an IC) comprising:
depositing a passivation layer on a first redistribution line (Fig. 1: dielectric stack 16, i.e., passivation layer 132 of instant application, is over conductive via/runner 20/18, i.e., RDL 124 of instant application; ¶0017: dielectric stack 16 composed of low dielectric constant material) and a second redistribution line (Fig. 1: dielectric stack 16 over conductive via/runner 22/19, i.e., second RDL 124), the first redistribution line extending along a semiconductor substrate (Fig. 1: via 20 has a conductive runner 18 which extends along semiconductor substrate), the second redistribution line extending along the semiconductor substrate (Fig. 1: via 22 has a conductive runner 19 which extends along semiconductor substrate), the passivation layer filling an entirety of an area between the first redistribution line and the second redistribution line in a cross-sectional view (Fig. 1: dielectric stack 16 fills the entire area between vias 20 and 22);
planarizing the passivation layer to have a planar top surface (¶0023: dielectric stack 16 is subjected to a chemical/mechanical polishing step to planarize the top surface 23), the planar top surface of the passivation layer extending continuously over … (a) the area between the first redistribution line and the second redistribution line in the cross-sectional view (Fig. 1: planar top surface 23 of dielectric stack 16 extends over area between vias 20 and 22),
forming a passive device on the planar top surface of the passivation layer (Fig. 5: passive device 14 is formed on a planar surface of dielectric stack 16, i.e., passivation layer), the passive device vertically overlapping the area between the first redistribution line and the second redistribution line in the cross-sectional view (Fig. 1: passive device 14 overlaps area between vias 20 and 22);
depositing a dielectric layer over the passive device and the passivation layer (See Figs. 5 and 6; Fig. 6: dielectric stack 24 is deposited over device 14 and dielectric stack 16); and
forming a first die connector and a second die connector (See Figs. 5 and 6; Fig. 6: conductive via/runner 40/42, i.e., first die connector, and via/runner 44/46, i.e., second die connector), the first die connector extending through the dielectric layer (Fig. 6: via/runner 40/42 extends through dielectric stack 24) and … (b), the first die connector physically and electrically coupled to the first redistribution line and to a first terminal of the passive device (Fig. 6: conductive via/runner 40/42 is physically and electrically coupled to electrically conductive via/runner 20/18 and to substrate 6; ¶0016: integrated circuit device 4 includes a semiconductor substrate 6 in which various devices, such as transistors (not shown) are formed, i.e., a first terminal),
the second die connector extending through the dielectric layer and … (c) (Fig. 6: via/runner 44/46 extends through dielectric stack 24) … the second die connector physically and electrically coupled to the second redistribution line and to a second terminal of the passive device (Fig. 6: conductive via/runner 44/46 is physically and electrically coupled to electrically conductive via/runner 22/19 and to substrate 6; ¶0016: semiconductor substrate 6 includes transistors (not shown), i.e., a second terminal).
However, Merchant does not specifically disclose wherein the passivation layer is over
(a) … the first redistribution line, the second redistribution line, and … a first portion of the passivation layer remaining over the first redistribution line after the passivation layer is planarized, a second portion of the passivation layer remaining over the second redistribution line after the passivation layer is planarized;
or wherein the first and second die connectors, respectively, extend through
(b) … the first portion of the passivation layer, …
(c) … the second portion of the passivation layer (132), ...
In a similar field of endeavor, Wu discloses wherein the passivation layer is over
(a) … the first redistribution line, the second redistribution line (Fig. 7A shows a buffer structure 204 over conductive lines 110A/110B, i.e., first and second redistribution lines), and … a first portion of the passivation layer remaining over the first redistribution line after the passivation layer is planarized (Fig. 7A shows a buffer structure 204 with a top layer 218 over conductive lines 110B, i.e., first redistribution line; ¶0024: a planarization operation, such as CMP may be performed to planarize the upper surfaces including layer 218), a second portion of the passivation layer remaining over the second redistribution line after the passivation layer is planarized (Fig. 7A shows a buffer structure with a top layer 218 over conductive line 110A, i.e., second redistribution line; ¶0024: a planarization operation, such as CMP may be performed to planarize the upper surfaces including layer 218);
and wherein the first (b) and second (c) die connectors, respectively, extend through
(b) … the first portion of the passivation layer (Fig. 11 shows a conductive via 322B, i.e., first die connector, extending through a first portion of buffer structure 204, i.e., passivation layer, and makes contact with conductive line 110B), …
(c) … the second portion of the passivation layer (Fig. 11 shows a conductive via 322A, i.e., second die connector, extending through a second portion of buffer structure 204, i.e., passivation layer, and makes contact with conductive line 110A), ...
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to modify Merchant to use Wu’s CMP endpoint. Merchant planarizes the interconnect until the conductive lines are exposed. Wu instead deposits a covering dielectric over the metal, planarizes that dielectric, and stops while a remaining portion still covers the conductive lines. Wu teaches doing so to protect the underlying metal and provide a planar surface for subsequent processing, while still permitting later vias through the remaining dielectric to the underlying lines. Applying that endpoint to Merchant would allow Merchant’s capacitor and vias to be formed on a protected, planar surface without exposing the metal during polish. The same vias Merchant already uses to contact the capacitor plates would then extend through the remaining passivation to the underlying lines, as Wu teaches.
Furthermore, Wu discloses a buffer structure over the metallization that is configured to protect the underlying lines if protrusions form on the conductive-line surfaces during later operations (See Wu, ¶0025). That teaching further supports leaving a covering dielectric over Merchant’s lines rather than exposing them at the CMP endpoint.
Re: Claim 29, the combination of Merchant and Wu discloses the method of claim 28.
Merchant also discloses wherein planarizing the passivation layer comprises performing a chemical mechanical polish on the passivation layer (¶0023: dielectric stack 16 subjected to CMP).
Re: Claim 30, the combination of Merchant and Wu discloses the method of claim 28.
Merchant also discloses further comprising:
forming an etch stop layer on the planar top surface of the passivation layer prior to forming the passive device (Fig. 2: barrier layer 28, i.e., etch-stop layer; ¶0022: barrier layer 28 serves as an etch stop layer), wherein the passive device physically contacts a top surface of the etch stop layer (Fig. 6: capacitor 14, i.e., passive device on layer 28).
Re: Claim 31, the combination of Merchant and Wu discloses the method of claim 28.
Merchant further discloses wherein forming the passive device comprises forming a plate capacitor (Fig. 6: capacitor 14), the plate capacitor comprising a lower metal plate (Fig. 2: bottom plate 30, i.e., lower metal plate),
an insulating layer on the lower metal plate (Fig. 3: capacitor dielectric layer 32, i.e., insulating layer, on lower plate 30), and
an upper metal plate on the insulating layer (Fig. 3: top plate 34, i.e., upper metal plate, on insulating layer 32).
Claims 18, 20, 32 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over MERCHANT et al. (US 20040061177 A1) in view of WU (US 20220216141 A1) and ZHOU et al. (US 20150264813 A1), hereinafter “Zhou.”
Re: Claim 18, the combination of Merchant and Wu discloses the method of claim 15.
However, the combination does not specifically disclose wherein forming the passive device comprises: forming a recess in the passivation layer; forming a first metal layer in the recess, a first pattern of the first metal layer defining a first metal via; depositing an insulating layer over the first metal layer; and forming a second metal layer over the insulating layer, a second pattern of the second metal layer defining a second metal via.
In a similar field of endeavor, Zhou discloses wherein forming the passive device comprises (See Figs. 1A-1C and 5B):
forming a recess in the passivation layer (Fig. 1A: trenches 102; ¶0035: Trenches 102 are formed in the interposing layer 100);
forming a first metal layer in the recess, a first pattern of the first metal layer defining a first metal via (Fig. 1A: conductive layer 104, i.e., first metal layer);
depositing an insulating layer over the first metal layer (Fig. 1B: dielectric layer 106, i.e., insulating layer over metal); and
forming a second metal layer over the insulating layer, a second pattern of the second metal layer defining a second metal via (Fig. 1B: conductive layer 108, i.e., second metal layer).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination of Merchant and Wu to conveniently provide different kinds of passive devices such as capacitors and resistors in an interposer structure (See Zhou, ¶0062).
Re: Claim 20, the combination of Merchant and Wu discloses the method of claim 15.
Merchant further discloses wherein forming the passive device comprises:
depositing an insulating layer over the metal layer (Fig. 1 shows a dielectric stack 24 over a passive device 14 having a metal layer 34).
However, the combination does not specifically disclose forming a metal layer over the passivation layer, a pattern of the metal layer defining a metal coil;
In a similar field of endeavor, Zhou discloses forming a metal layer over the passivation layer (Fig. 7: inductor 40), a pattern of the metal layer defining a metal coil (Fig. 7: inductor 40 is a metal coil);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination of Merchant and Wu to conveniently provide different kinds of passive devices such as capacitors and resistors in an interposer structure (See Zhou, ¶0062).
Re: Claim 32, the combination of Merchant and Wu discloses the method of claim 28.
However, the combination does not specifically disclose wherein forming the passive device comprises forming a deep-trench capacitor by patterning a recess in the passivation layer, forming an outer metal via in the recess, forming an insulating layer on the outer metal via, and forming an inner metal via on the insulating layer.
In a similar field of endeavor, Zhou discloses wherein forming the passive device comprises forming a deep-trench capacitor by patterning a recess in the passivation layer (See Figs. 1A-1C and 5B; Fig. 1A: trenches 102; ¶0009: capacitor is embedded in or disposed on the interposing layer),
forming an outer metal via in the recess (Fig. 1B: via 104a, i.e., outer metal via in trench 102),
forming an insulating layer on the outer metal via (ig. 1B: dielectric layer 106, i.e., insulating layer on metal), and
forming an inner metal via on the insulating layer (Fig. 1B: via 108, i.e., inner metal via on dielectric layer 106).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination of Merchant and Wu to conveniently provide different kinds of passive devices such as capacitors and resistors in an interposer structure (See Zhou, ¶0062).
Re: Claim 34, the combination of Merchant and Wu discloses the method of claim 28.
Merchant further discloses forming an insulating layer over the patterned metal layer.
However, the combination of Merchant and Wu does not disclose wherein forming the passive device comprises forming an inductor by forming a patterned metal layer that defines a metal coil.
In a similar field of endeavor, Zhou discloses wherein forming the passive device comprises forming an inductor by forming a patterned metal layer that defines a metal coil (Fig. 7: inductor 40 is a metal coil).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination of Merchant and Wu to conveniently provide different kinds of passive devices such as capacitors and resistors in an interposer structure (See Zhou, ¶0062).
Claims 19 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over MERCHANT et al. (US 20040061177 A1) in view of WU (US 20220216141 A1) and ALCORN et al. (US 20210375856 A1), hereinafter “Alcorn.”
Re: Claim 19, the combination of Merchant and Wu discloses the method of claim 15.
While Wu discloses that various passive devices may be formed such as capacitors, inductors, diodes and resistors (See Wu, ¶0012), the combination of Merchant and Wu does not specifically show wherein forming the passive device comprises: forming a first metal layer over the passivation layer, the first metal layer being unpatterned; depositing an insulating layer over the first metal layer; and forming a second metal layer over the insulating layer, a pattern of the second metal layer defining a metal wire.
In a similar field of endeavor, Alcorn discloses wherein forming the passive device comprises (¶0096: methods of fabricating passive devices, i.e., resistive components such as resistors 375r; ¶0097: fabricated using standard semiconductor processing techniques such as thin film and/or photolithography processing):
forming a first metal layer over the passivation layer, the first metal layer being unpatterned (Fig. 6A: backmetal 345; ¶0098: FIG. 6A, after forming a first backmetal layer 345 in FIG. 5E, an insulator layer 370 is formed on the first backmetal layer 345);
depositing an insulating layer over the first metal layer (Fig. 6A: insulator layer 370; See ¶0098: insulator layer 370 is formed on the first backmetal layer 345); and
forming a second metal layer over the insulating layer, a pattern of the second metal layer defining a metal wire (Fig. 6A: resistor 375r; ¶0098: passive devices 375 are formed on the insulator layer 370, for example, by forming and patterning a second backmetal layer to define one or more... discrete resistors 375r, e.g., defined by portions of the second backmetal layer patterned to define resistive segments.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination of Merchant in view of Wu in order to design a resistive structure such as a resistor to reduce or eliminate complexities associated with off-chip connections (e.g., using wire bonds) to matching circuitry (See Alcorn, ¶0054).
Re: Claim 33, the combination of Merchant and Wu discloses the method of claim 28.
While Wu discloses that various passive devices may be formed such as capacitors, inductors, diodes and resistors (See Wu, ¶0012), the combination of Merchant and Wu does not specifically show wherein forming the passive device comprises forming a resistor by forming a lower metal layer over the passivation layer, forming an insulating layer on the lower metal layer, and forming a patterned upper metal layer over the insulating layer, the patterned upper metal layer defining a metal wire.
In a similar field of endeavor, Alcorn discloses wherein forming the passive device comprises (See ¶0096: methods of fabricating passive devices, i.e., resistive components such as resistors 375r; See ¶0097) forming a resistor by forming a lower metal layer over the passivation layer (Fig. 6A: backmetal 345; ¶0098: FIG. 6A, after forming a first backmetal layer 345 in FIG. 5E, an insulator layer 370 is formed on the first backmetal layer 345),
forming an insulating layer on the lower metal layer (Fig. 6A: insulator layer 370; See ¶0098: insulator layer 370 is formed on the first backmetal layer 345), and
forming a patterned upper metal layer over the insulating layer, the patterned upper metal layer defining a metal wire (Fig. 6A: resistor 375r; ¶0098: passive devices 375 are formed on the insulator layer 370, for example, by forming and patterning a second backmetal layer to define one or more... discrete resistors 375r, e.g., defined by portions of the second backmetal layer patterned to define resistive segments.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the combination of Merchant in view of Wu in order to design a resistive structure such as a resistor to reduce or eliminate complexities associated with off-chip connections (e.g., using wire bonds) to matching circuitry (See Alcorn, ¶0054).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over MERCHANT et al. (US 20040061177 A1) in view of WU (US 20220216141 A1) and CHEN et al. (US 20220223550 A1), hereinafter “Chen.”
Re: Claim 25, the combination of Merchant and Wu discloses the method of claim 21.
Merchant teaches the two RDL’s in a passivation later (Fig. 1: vias/runners 20/18 and 22/19, dielectric stack 16) and planarizing the passivation/dielectric stack. However, the combination of Merchant and Wu does not specifically disclose further comprising: depositing a second passivation layer over the semiconductor substrate, wherein the first redistribution line and the second redistribution line are each formed over the second passivation layer, wherein the planar top surface of the first passivation layer has a higher degree of planarity than a top surface of the second passivation layer.
In a similar field of endeavor, Chen discloses further comprising:
depositing a second passivation layer over the semiconductor substrate (Fig. 2 shows a first passivation layer 60B, i.e., layer 132 of the instant application which corresponds to layer 16 of the Merchant’s Fig. 1, and second passivation layer 60A, i.e., layer 118 of the instant application.),
wherein the first redistribution line and the second redistribution line are each formed over the second passivation layer (Fig. 3 shows first and second RDL’s 66 formed in openings 64 over the second passivation layer 60A which is on the interconnect structure 54; See ¶0019),
wherein the planar top surface of the first passivation layer has a higher degree of planarity than a top surface of the second passivation layer (Fig. 2 shows a first passivation layer 60B; Merchant discloses a single planarization step performed on the top passivation layer, i.e., first passivation layer 60B/dielectric stack 16. ; In other words, incorporating the two layers of Chen into the structure of Merchant would create two layers (60B/60A) with the top layer, i.e., first passivation layer 60B, having a higher degree of planarity then the lower layer, i.e., second passivation layer 60A, due to the CMP step of Merchant on the top layer.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the method of Merchant to include a second passivation layer deposited on the interconnect structure as disclosed by Chen. One would be motivated to form Merchant’s conductive lines on a lower passivation as disclosed by Chen to provide a higher degree of isolation to the redistribution lines, the contact pads/terminals, and the passive devices above the redistribution layers (See Chen, ¶¶0016 and 0019-0020).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
FISCHER (US 20100224960 A1): Fig. 2 shows a structure having multiple passivation layers surrounding RDL’s with a passive device in between the two RDL’s.
ZHANG et al. (US 20120187539 A1): Fig. 3A shows a structure with multiple passivation/dielectric layers (48, 50, 52); Figs. 3C and 3D show relevant steps in the formation of a RDL through multiple passivation/dielectric layers to reach the lower via lines; Fig. 3F shows the structure after the manufacturing steps have been completed. Fig. 4 shows an inductor. Fig. 5E shows two integrated circuit wafers aligned and coupled in a 3D IC wafer stack like Fig. 16 of the applicant’s specification.
LI (US 20190341347 A1): Fig. 9 shows a structure relevant to limitations claimed in the current application.
YAMAZAKI et al. (US 20060130303 A1): Figs. 3D-3F show manufacturing steps relevant to limitations claimed in the current application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights