DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on February 4, 2026.
Claim 12 is amended. No claims are canceled. No claims are added.
Response to Arguments
3. Applicant's arguments filed February 4, 2026, have been fully considered but they are not persuasive. Therefore, the 35 USC § 103 rejection set forth in the previous Office Action is maintained.
Applicant effectively asserts on page 10 that amending a limitation into claim 12 that made claims 1 and/or 18 allowable should therefore make claim 12 allowable. However, claims 1 and 18 contain additional, significant limitations not included in claim 12. A limitation not taught in the prior art within the context of claims 1 and 18 cannot be used in isolation in a substantively different claim to make it allowable.
Specifically, claims 1 and 18 further constrain the ordering of memory array elements by including the relative positioning of the I/O circuit (FIG. 2, 112). Claim 12 makes no mention of the I/O circuit or allusion to its positioning.
Figure A, which follows, illustrates how FIG. 5 of Raj, et al (US 20230290387 A1, hereinafter Raj), teaches the ordering of elements of claim 12 in the present application.
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Figure A: FIG. 5 of Raj compared to Applicant claim 12.
Therefore, Applicant’s arguments are not persuasive and the 35 USC § 103 rejection set forth in the previous Office Action is maintained.
Note that the inclusion of an input/output (I/O) circuit physically disposed next to the memory array along a first lateral direction, as recited in claims 1 and 18 but absent in claim 12, would further constrain the ordering of elements. One example of the ordering constraint of claim 1 is illustrated in Figure B, which follows.
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Figure B: Raj, FIG. 5, compared to Applicant claim 1.
Referencing Figure B, by positioning the I/O circuit next to the bottom of the memory array, the First Portion does not interpose the I/O circuit and First Pre-Charge circuit, as recited in claim 1. If the I/O circuit were moved next to the top of the array, it would no longer be opposite the First Portion.
While the assignments of the first and second portions and first and second pre-charge circuits may be changed, Examiner believes each assignment fails to teach the limitations of claim 1 due to the additional constraint of the I/O Circuit. For example, if the First and Second Portions were swapped, the First Portion would interpose the I/O Circuit and the First Pre-charge circuit, but the Second Portion would no longer interpose the First and Second Pre-Charge circuits. For this reason, claims 1 and 18 are indicated to be allowable while claim 12 remains rejected.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 12, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Raj, et al (US 20230290387 A1) hereinafter Raj, in view of Pao, et al (US 20220406372 A1), hereinafter Pao.
Regarding independent claim 12, Raj teaches a memory circuit (FIGS. 1-5; ¶ [0009-0013]), comprising:
a memory array (FIG. 5, CORE_TOP, CORE_BOT; ¶ [0025] teaches cells of cores are arranged in rows and columns) comprising a first portion (FIG. 5, CORE_TOP) and a second portion (FIG. 5, CORE_BOT), wherein the first portion comprises a plurality of first memory cells (¶ [0025], [0052]) that are coupled to one another through a first bit line (FIG. 5, bl_top, blb_top), and the second portion comprises a plurality of second memory cells (¶ [0025], [0052]) that are coupled to one another through a second bit line (FIG. 5, bl_bot, blb_bot), and wherein the first bit line extends along a first lateral direction (i.e., vertical – the direction in which the pre-charge circuits and memory cores are stacked in FIG. 5) and the second bit line includes at least a portion extending along the first lateral direction (FIG. 5, both first and second bit lines extend vertically);
a first pre-charge circuit (FIG. 5, P10-P12) physically disposed next to the first portion such that the first pre-charge circuit interposes the first portion and the second portion along the first lateral direction (FIG. 5, P10-P12 is interposed – stacked vertically in between – the first and second portions of the memory array), wherein the first pre-charge circuit is configured to charge the first bit line to a logic high state (FIG. 5, VDD coupled to P10 and P11 for the purpose of supplying bit lines bl_top and blb_top; ¶ [0053]); and
a second pre-charge circuit (FIG. 5, P13-P15) physically disposed next to the second portion and opposite from the first pre-charge circuit along the first lateral direction (FIG. 5, P13-P15 is stacked vertically next to (below) the second portion of the memory array (CORE_BOT)), such that the second portion interposes the first pre-charge circuit and the second pre-charge circuit (FIG. 5, second portion (CORE_BOT) interposes the first pre-charge circuit (FIG. 5, P10-12) and the second pre-charge circuit (FIG. 5, P13-P15) – see also Figure A), wherein the second pre-charge circuit is configured to charge the second bit line to the logic high state (FIG. 5, VDD coupled to P13 and P14 for the purpose of supplying bit lines bl_bot and blb_bot; ¶ [0053]).
Raj does not explicitly teach pre-charging the first bit lines occurs before accessing the plurality of first memory cells and pre-charging the second bit lines occurs before accessing the plurality of second memory cells.
Pao teaches in Figure 3 bit lines are pre-charged prior to cell access time T0-T1 and therefore Raj as modified by Pao teaches pre-charging the first bit lines occurs before accessing the plurality of first memory cells and pre-charging the second bit lines occurs before accessing the plurality of second memory cells.
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Pao into the method of Raj to include pre-charging bit lines prior to accessing cells associated with those bit lines (Pao Figure 3). The ordinary artisan would have been motivated to modify Raj in the above manner for the purpose of enabling a sense amplifier to sense the difference between two bit lines when a memory cell pulls a particular one of the bit lines low, outputting a corresponding data value accordingly (Pao, ¶ [0012]).
Regarding claim 15, Raj as modified by Pao teaches the limitations of claim 12.
Raj further teaches a first control line (FIG. 5, pre_top coupled to gates of P10-P12) extending in a second lateral direction (i.e., horizontal) perpendicular to the first lateral direction and operatively coupled to the first pre-charge circuit (FIG.5, pre_top extends both horizontally to P10 and P11 and vertically to P12);
a second control line (FIG. 5, pre_top coupled to gates of P13-P15) extending in the second lateral direction and operatively coupled to the second pre-charge circuit (FIG. 5, pre_top extends both horizontally to P13 and P14 and vertically to P15),
wherein the first control line is operatively coupled to the second control line via a third control line extending in the first lateral direction (FIG. 5, segments of pre_top are connected together as indicated by the common node/signal name, which is equivalent to extending the vertical line from the gate of P12 to the gate of P15 (note Applicant teaches in ¶ [0074] of the present application that “the first, second, or third control lines can refer to portions or segments of a single control line” (see Fig. 2, 208 in the present application))).
Regarding claim 17, Raj as modified by Pao teaches the limitations of claim 12.
Raj further teaches at least one of:
the first pre-charge circuit comprises a first transistor operating as a switch for charging the first bit line to the logic high state according to a gate voltage (FIG. 5, e.g., transistor P10 operates as a switch to charge bl_top via supply VDD according to its gate voltage); or the second pre-charge circuit comprises a second transistor operating as a switch for charging the second bit line to the logic high state according to a gate voltage.
8. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Raj, et al (US 20230290387 A1) hereinafter Raj, in view of Pao, et al (US 20220406372 A1), hereinafter Pao, and further in view of Jain, et al (US 20210200462 A1), hereinafter Jain.
Regarding claim 16, Raj as modified by Pao teaches the limitations of claim 15.
Raj does not teach
a first buffer disposed in the first control line;
a first inverter disposed in the first control line;
a second buffer disposed in the second control line; and
a second inverter disposed in the second control line.
Jain teaches in FIG. 9 a first buffer disposed in the first control line (e.g., inverter buffer 902; ¶ [0038]);
a first inverter disposed in the first control line (902 provides both inverting and buffering functions);
a second buffer disposed in the second control line (e.g., inverter buffer 904; ¶ [0038]); and
a second inverter disposed in the second control line (904 provides both inverting and buffering functions).
(Note Jain also teaches non-inverting buffers (e.g., FIG. 2, 208). Whether or not an inverter is included in a signal path depends on the desired logic sense for that signal.)
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Jain into the device of Raj to include a buffer in control lines. The ordinary artisan would have been motivated to modify Raj in the above manner for the purpose of propagating (driving) command signals (Jain ¶ [0038]).
9. Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Raj, et al (US 20230290387 A1) hereinafter Raj, in view of Pao, et al (US 20220406372 A1), hereinafter Pao, and further in view of Liaw (US 9558809 B1).
Regarding claim 13, Raj as modified by Pao teaches the limitations of claim 12.
Raj further teaches the first bit line extends to the first pre-charge circuit (FIG. 5 shows, e.g., bl_top extending from CORE_TOP to the first pre-charge circuit of P10-P12) and the second bit line extends to the second pre-charge circuit (FIG. 5 shows, e.g., bl_bot extending from CORE_BOT to the second pre-charge circuit of P13-P15).
Raj does not teach the first bit line is disposed in a first metallization layer, and the second bit line includes a first segment and a second segment, in which the first segment is disposed in a second metallization layer and the second segment is disposed in the first metallization layer.
Liaw teaches the first bit line (FIG. 6, BL3) is disposed in a first metallization layer (BL3 may be considered to be in the “first” metallization layer), the second bit line (FIG. 6, BL4 connected to BL1) includes a first segment (FIG. 6, BL1) and a second segment (FIG. 6, BL4), in which the first segment is disposed in a second metallization layer (FIG. 7A, BL3 is shown in a different layer than BL1, and so BL1 may be considered to be in the “second” metallization layer) and the second segment is disposed in the first metallization layer (Col. 7, l. 66 – Col. 8, l. 2 teach BL4 and BL3 may be in the same metal layer; because BL3 is in the first metallization layer, second segment BL4 is also in the first metallization layer).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Liaw into the device of Raj to include forming the bitline and the complementary bitline in the subarray farther from the I/O circuits by a metal layer disposed in the first metal layer level (Liaw Col. 20, ll. 32-39). The ordinary artisan would have been motivated to modify Raj in the above manner for the purpose of lowering the overall resistance and coupling capacitance of the bitline, thereby increasing an operation speed of SRAM (Liaw Col. 20, ll. 39-42).
Regarding claim 14, Raj as modified by Pao and Liaw teaches the limitations of claim 13.
Liaw further teaches the second metallization layer is disposed above the first metallization layer (FIG. 7A, BL3 is shown in a different layer than BL1, and so the second metallization layer of BL1 may be considered to be “above” the first metallization layer of BL3 (Examiner notes 'above' is a relative term that depends on the orientation of the device and the designation of which direction is 'above' is arbitrary)).
Allowable Subject Matter
10. The following is a statement of reasons for the indication of allowable subject matter.
Regarding independent claim 1, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a second pre-charge circuit physically disposed opposite the second portion from the first pre-charge circuit such that the second portion interposes the first pre-charge circuit and the second pre-charge circuit along the first lateral direction. Claims 2-11 depend on claim 1.
Regarding independent claim 18, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of forming a second pre-charge circuit physically disposed opposite the second portion from the first pre-charge circuit such that the second portion interposes the first pre-charge circuit and the second pre-charge circuit along the first lateral direction. Claims 19-20 depend on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827 /AMIR ZARABIAN/ Supervisory Patent Examiner, Art Unit 2827