Prosecution Insights
Last updated: October 01, 2026
Application No. 18/434,553

DEVICE OF DIELECTRIC LAYER

Final Rejection §103
Filed
Feb 06, 2024
Priority
Sep 29, 2017 — provisional 62/565,696 +2 more
Examiner
DINKE, BITEW A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
572 granted / 785 resolved
+4.9% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
52 currently pending
Career history
816
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
65.8%
+25.8% vs TC avg
§102
8.1%
-31.9% vs TC avg
§112
11.8%
-28.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 785 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1, 9, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 and 5- 8 are rejected under 35 U.S.C. 103 as being unpatentable over Canaperi et al. (U.S. 2015/0287593 A1, hereinafter refer to Canaperi). Regarding Claim 1: Canaperi discloses a device (see Canaperi, Figs.3 and 7 as shown below and ¶ [0001]) comprising: PNG media_image1.png 344 569 media_image1.png Greyscale PNG media_image2.png 484 796 media_image2.png Greyscale a first dielectric layer (738/772) (see Canaperi, Fig.7 as shown above); a first conductor (740) in the first dielectric layer (738/772) (see Canaperi, Fig.7 as shown above); an etch stop layer (762/multilayer dielectric film) over the first dielectric layer (738/772) (see Canaperi, Fig.7 as shown above and ¶ [0039]), the etch stop layer (762) has a first surface facing the first dielectric layer (738/772) and a second surface facing away from the first dielectric layer (738/772) (see Canaperi, Fig.7 as shown above), and a second dielectric layer (744) over the etch stop layer (762) (see Canaperi, Fig.7 as shown above); and a second conductor (750) in the second dielectric layer (744) and etch stop layer (762) and electrically connected to the first conductor (740) (see Canaperi, Fig.7 as shown above). The first embodiment of Canaperi (Fig.7), is silent upon explicitly disclosing wherein the etch stop layer comprises a plurality of first sub-layers and a plurality of second sub-layers alternately stacked, the first sub-layers comprise Si-Si bonds and are substantially free of Si-C-Si bonds, the second sub-layers comprise Si-C-Si bonds, a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. However, the fifth embodiment of Canaperi (Fig.3), teaches wherein the etch stop layer (300/multilayer dielectric film) comprises a plurality of first sub-layers (304/308) and a plurality of second sub-layers (302/306) alternately stacked, the first sub-layers (304/308) comprise Si-Si bonds (note: silicon dioxide were known to have a Si-Si bonds) and are substantially free of Si-C-Si bonds, the second sub-layers (302/306) comprise Si-C-Si bonds (note: SiCNOx were known to have a Si-C-Si bonds) (see Canaperi, Fig.3 as shown above, Embodiment #5 Table, and ¶ [0030]- ¶ [0031]), a concentration of carbon in the etch stop layer (300) periodically varies from the first surface to the second surface (see Canaperi, Fig.3 as shown above, Embodiment #5 Table, and ¶ [0030]- ¶ [0031]). Note: it is an obvious matter of design choice to arrange either sublayer 308 directly on the first dielectric layer or sublayer 302 directly on the first dielectric layer. Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of first embodiment of Canaperi (Fig.7) and fifth embodiment of Canaperi (Fig.3) to enable the etch stop layer of first embodiment of Canaperi (Fig.7) to be formed according to the teachings of fifth embodiment of Canaperi (Fig.3) in order to obtain a multilayer dielectric film. Regarding Claim 2: Canaperi as modified teaches a device as set forth in claim 1 as above. The modification of Canaperi further teaches wherein a concentration of oxygen in the etch stop layer (300) periodically varies from the first surface to the second surface (see Canaperi, Fig.3 as shown above, Embodiment #5 Table, and ¶ [0030]- ¶ [0031]). Note: it is an obvious matter of design choice to arrange either sublayer 308 directly on the first dielectric layer or sublayer 302 directly on the first dielectric layer. Regarding Claim 3: Canaperi as modified teaches a device as set forth in claim 1 as above. The modification of Canaperi further teaches wherein a concentration of nitrogen in the etch stop layer (300) periodically varies from the first surface to the second surface (see Canaperi, Fig.3 as shown above, Embodiment #5 Table, and ¶ [0030]- ¶ [0031]). Note: it is an obvious matter of design choice to arrange either sublayer 308 directly on the first dielectric layer or sublayer 302 directly on the first dielectric layer. Regarding Claim 5: Canaperi as modified teaches a device as set forth in claim 1 as above. The modification of Canaperi further teaches wherein the etch stop layer (300) further comprises Si-C-O (see Canaperi, Fig.3 as shown above, Embodiment #5 Table, and ¶ [0030]- ¶ [0031]). Regarding Claim 6: Canaperi as modified teaches a device as set forth in claim 1 as above. The modification of Canaperi further teaches wherein the etch stop layer (300) further comprises Si-C-N (see Canaperi, Fig.3 as shown above, Embodiment #5 Table, and ¶ [0030]- ¶ [0031]). Regarding Claim 7: Canaperi as modified teaches a device as set forth in claim 1 as above. The modification of Canaperi further teaches wherein the concentration of carbon in the etch stop layer (300) increases from the first surface to an intermediate position within the etch stop layer (300) and then decreases from the intermediate position to the second surface of the etch stop layer (300) (note: ordinary skill in the art capable of determining the concentration of carbon in the etch stop layer by utilizing the Canaperi’s method) (see Canaperi, Fig.3 as shown above, Embodiment #5 Table, and ¶ [0030]- ¶ [0031]). Regarding Claim 8: Canaperi as modified teaches a device as set forth in claim 7 as above. The modification of Canaperi further teaches wherein a concentration of nitrogen in the etch stop layer (300) increases while the concentration of carbon decreases (note: ordinary skill in the art capable of determining the concentration of carbon in the etch stop layer by utilizing the Canaperi’s method) (see Canaperi, Fig.3 as shown above, Embodiment #5 Table, and ¶ [0030]- ¶ [0031]). Claim(s) 9 -21 are rejected under 35 U.S.C. 103 as being unpatentable over Ide et al. (U.S. 2009/0152686 A1, hereinafter refer to Ide). Regarding Claim 9: Ide discloses a device (see Ide, Fig.7 as shown below and ¶ [0096]) comprising: PNG media_image3.png 508 731 media_image3.png Greyscale a first conductor (74A) (see Ide, Fig.7 as shown above); a first nitride layer (77/SiN or SiCN) over the first conductor (74A) (see Ide, Fig.7 as shown above and ¶ [0096]); a first oxide layer (78) on and in contact with the first nitride layer (77) (see Ide, Fig.7 as shown above and ¶ [0096]); a second nitride layer (79/SiN or SiCN) on and in contact with the first oxide layer (78) (see Ide, Fig.7 as shown above and ¶ [0096]); a second oxide layer (80) on and in contact with the second nitride layer (79), wherein the first oxide layer (78) and the second oxide layer (80) comprise Si-C-Si bonds (see Ide, Fig.7 as shown above and ¶ [0096]); a dielectric layer (86/87/88/89) over the second oxide layer (80) (see Ide, Fig.7 as shown above and ¶ [0102]); and a second conductor (86a/86A/76A/78A/80A/82A/84A) in the dielectric layer (86/87/88/89) and electrically connected to the first conductor (74A), wherein the second conductor (86a/86A/76A/78A/80A/82A/84A) has opposite sidewalls in contact with inner sidewalls of the first nitride layer (77), the first oxide layer (78), the second nitride layer (79) and the second oxide layer (80) (see Ide, Fig.7 as shown above). Note: Ide teaches a laundry list of materials including SiN and SiCN for forming the alternatively stacked etch stop layers as shown above. Hence, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to select the known SiN or SiCN material for the first and the second nitride layers for forming nitride and oxide stacked etch stop layer (for support see Kageyama (U.S. 2009/0115062 A1, hereinafter refer to Kageyama), which teaches, an etching stopper film 15 having a laminated structure of an SiCO layer and an SiCN layer (see Kageyama, ¶ [0043])), since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416. Regarding Claim 10: Ide as modified teaches a device as set forth in claim 9 as above. The modification of Ide further teaches wherein the opposite sidewalls of the second conductor (86a/86A/76A/78A/80A/82A/84A) are in contact with inner sidewalls of the dielectric layer (86/87/88/89) (see Ide, Fig.7 as shown above). Regarding Claim 11: Ide as modified teaches a device as set forth in claim 9 as above. The modification of Ide further teaches wherein top ends of opposite sidewalls of the dielectric layer (86/87/88/89) are at different heights (see Ide, Fig.7 as shown above). Regarding Claim 12: Ide as modified teaches a device as set forth in claim 9 as above. The modification of Ide further teaches wherein a third oxide layer (76) directly between the first conductor (74A) and the first nitride layer (77) (see Ide, Fig.7 as shown above). Regarding Claim 13: Ide as modified teaches a device as set forth in claim 9 as above. The modification of Ide further teaches wherein the dielectric layer (81/82/83/84/85/86/87/88/89) is directly over the second oxide layer (80) (see Ide, Fig.7 as shown above). Regarding Claim 14: Ide as modified teaches a device as set forth in claim 13 as above. The modification of Ide further teaches wherein the dielectric layer (89) is a nitride layer (see Ide, Fig.7 as shown above and ¶ [0104]). Regarding Claim 15: Ide discloses a device (see Ide, Fig.7 as shown above and ¶ [0096]) comprising: a first dielectric layer (74/75) (see Ide, Fig.7 as shown above); a first conductor (74A) in the first dielectric layer (74/75) (see Ide, Fig.7 as shown above); a multilayer dielectric stack over the first conductor and having a plurality of oxide layers (78/80/82/84) and nitride layers (77/79/81/83/85, SiN or SiCN) arranged alternately, wherein the oxide layers (78/80/82/84) of the multilayer dielectric stack comprise Si-C-Si bonds (see Ide, Fig.7 as shown above and ¶ [0096]); a second dielectric layer (86/87/88) over the multilayer dielectric stack, wherein the second dielectric layer (86/87/88) has a material different from a topmost layer of the multilayer dielectric stack (85) (see Ide, Fig.7 as shown above, ¶ [0096], and ¶ [0102]); and a second conductor (86a/86A/76A/78A/80A/82A/84A/89A) extending through the second dielectric layer (86/87/88) and the multilayer dielectric stack to the first conductor (74A) (see Ide, Fig.7 as shown above). Note: Ide teaches a laundry list of materials including SiN and SiCN for forming the alternatively stacked etch stop layers as shown above. Hence, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to select the known SiN or SiCN material for the nitride layers for forming nitride and oxide stacked etch stop layer (for support see Kageyama (U.S. 2009/0115062 A1, hereinafter refer to Kageyama), which teaches, an etching stopper film 15 having a laminated structure of an SiCO layer and an SiCN layer (see Kageyama, ¶ [0043])), since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416. Regarding Claim 16: Ide as modified teaches a device as set forth in claim 15 as above. The modification of Ide further teaches wherein the multilayer dielectric stack overlaps an interface between the first dielectric layer (74/75) and the first conductor (74A) (see Ide, Fig.7 as shown above). Regarding Claim 17: Ide as modified teaches a device as set forth in claim 15 as above. The modification of Ide further teaches a third conductor (74B) in the first dielectric layer (74/75), wherein the second conductor (86a/86A/76A/78A/80A/82A/84A/89A) extends over the second dielectric layer (86/87/88) to the third conductor (a via portion of conductor 76A) (see Ide, Fig.7 as shown above). Regarding Claim 18: Ide as modified teaches a device as set forth in claim 15 as above. The modification of Ide further teaches wherein the second conductor (86a/86A/76A/78A/80A/82A/84A/89A) has opposite sidewalls in contact with inner sidewalls of the oxide layers (78/80/82/84) and the nitride layers (77/79/81/83/85, SiN or SiCN) of the multilayer dielectric stack (see Ide, Fig.7 as shown above). Regarding Claim 19: Ide as modified teaches a device as set forth in claim 18 as above. The modification of Ide further teaches wherein the opposite sidewalls of the second conductor (86a/86A/76A/78A/80A/82A/84A/89A) are in contact with inner sidewalls of the second dielectric layer (86/87/88) (see Ide, Fig.7 as shown above). Regarding Claim 20: Ide as modified teaches a device as set forth in claim 15 as above. The modification of Ide further teaches wherein the topmost layer (85) and a bottommost layer (77) of the multilayer dielectric stack have the same material (see Ide, Fig.7 as shown above). Regarding Claim 21: Ide as modified teaches a device as set forth in claim 15 as above. The modification of Ide further teaches wherein the nitride layers (77/79/81/83/85, SiCN) of the multilayer dielectric stack are substantially free of Si-C-Si bonds (see Ide, Fig.7 as shown above and ¶ [0096]). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BITEW A DINKE/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Feb 06, 2024
Application Filed
May 13, 2026
Non-Final Rejection mailed — §103
Aug 12, 2026
Response Filed
Aug 28, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
85%
With Interview (+12.4%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 785 resolved cases by this examiner. Grant probability derived from career allowance rate.

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