DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on June 22nd, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Election/Restrictions
Applicant's election without traverse of Group I and Species A directed to Fig. 1-10E (claims 1-6, 8-12 and 21-29) in the reply filed on June 22nd, 2026 is acknowledged.
Claim Objections
Claims 8, 11-12, 22, and 28 are objected to because of the following informalities:
Claim 8 recites “the semiconductor fins” in lines 6 and 9 refers back to “a plurality of semiconductor fins” in lines 2 and should be amended to “the plurality of semiconductor fins” for avoiding confusion. Appropriate correction is required.
Claim 8 recites “the oxide layers” in lines 8 and 11 refers back to “a plurality of oxide layers” in line 5 and should be amended to “the plurality of oxide layers” for avoiding confusion. Appropriate correction is required.
Claim 11 recites “the semiconductor fins” in line 2 refers back to “a plurality of semiconductor fins” in lines 2 of claim 8 and should be amended to “the plurality of semiconductor fins” for avoiding confusion. Appropriate correction is required.
Claim 11 recites “the oxide layers” in lines 2-3 refers back to “a plurality of oxide layers” in line 5 of claim 8 and should be amended to “the plurality of oxide layers” for avoiding confusion. Appropriate correction is required.
Claim 11 recites “the isolation regions” in line 3 refers back to “a plurality of isolation regions” in line 1 and should be amended to “the plurality of isolation regions” for avoiding confusion. Appropriate correction is required.
Claim 12 recites “the oxide layers” in lines 2 and 3 refers back to “a plurality of oxide layers” in line 5 of claim 8 and should be amended to “the plurality of oxide layers” for avoiding confusion. Appropriate correction is required.
Claim 22 recites “the exposed surfaces” in line 3 refers back to “an exposed surface of the patterned dummy gate structure” in line 7 of claim 21 and should be amended to “the exposed surface of the patterned dummy gate structure” for avoiding confusion. Appropriate correction is required.
Claim 28 recites a typo “the gate spacers have stepped sidewall structure etch” in line 1-2 and should delete the word “etch” for avoiding confusion. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-6 and 8-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites “a surface modification layer over the gate layer” in lines 5-6. According to Applicant’s specification, the surface modification layer formed on the exposed sidewall of gate layer 110 but not over the top surface of gate layer 110 (see Applicant’s Fig. 7A and [0039]). Therefore, it is unclear to the examiner how can the surface modification layer be over the gate layer.
Claim 1 recites “forming a gate structure over the semiconductor fin and extending between the source/drain regions and in the surface modification layer” in lines 9-10. According to Applicant’s specification, the gate structure 132 comprising gate dielectric layer 34 and work function metal layer 36 extending under the surface modification layer 150, but not in the surface modification layer 150 (see Applicant’s Fig. 10D and [0067]). Therefore, it is unclear to the examiner how can the gate structure extending in the surface modification layer.
Claims 2-6 are rejected for depending on claim 1 and having the above issues incorporated into the claims.
Claim 8 recites “a plurality of oxide layers over the patterned gate layer” in line 5. According to Applicant’s specification, the surface modification layer comprises a plurality of oxide layers formed on the exposed sidewall of gate layer 110 but not over the top surface of gate layer 110 (see Applicant’s Fig. 7A and [0039]). Therefore, it is unclear to the examiner how can the plurality of oxide layers be over the gate layer.
Claims 9-12 are rejected for depending on claim 8 and having the above issues incorporated into the claims.
Allowable Subject Matter
Claims 21, 24-27, and 29 are allowed over prior art of record and claim 22 and 28 will also be allowed if amend to overcome the objections as set forth in the office action above.
The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following:
Regarding claim 21, Wu et al. (Pub. No.: US 2024/0405097 A1 B2) discloses a method in Figs. 1-10F comprising: forming a semiconductor fin structure (104a) over a substrate (102); forming an isolation region (106) around the semiconductor fin structure; forming a patterned dummy gate structure (130) over the semiconductor fin structure and the isolation region; performing a surface modification process (oxidizing process) to the patterned dummy gate structure to form a surface modification layer (110) on an exposed surface of the patterned dummy gate structure (see Figs. 6A-6C); forming gate spacers (125); forming source/drain regions (135) on opposite ends of the semiconductor fin structure; removing the patterned dummy gate structure to form a gate trench (150) between the gate spacers (see column 5, lines 12 through column 14, line 63).
Wang et al. (Pub. No.: US 2021/0272850 A1) discloses a method in Figs. 4A-17 comprising: forming a gate dielectric layer (25) over a plurality of semiconductor fins (15); forming a gate layer (silicon of layer 30) over the gate dielectric layer; patterning the gate layer (30); forming a plurality of oxide layers (45) over the patterned gate layer wherein the semiconductor fins are covered by the gate dielectric when oxidizing the gate layer; forming a spacer (50) over the oxide layers and the gate dielectric layer; forming source/drain regions (35) on the semiconductor fins; removing the gate dielectric layer and the gate layer (see Fig. 11); and forming a gate structure (80/85/110) between the oxide layers (see Fig. 17 and [0033-0076]).
The combination of Wu et al. and Wang et al. fails to disclose forming the gate spacers over the surface modification layer and form gaps between sidewalls of the source/drain regions, a top surface of the isolation region, and the surface modification layer, wherein a gate electrode of the replacement gate structure is out of the gaps as recited in claim 21. Claims 22-29 depend on claim 21, and therefore also include said claimed limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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