Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 06/17/26. Claims 1-20 are pending in this application.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 and 18-20 are rejected under 35 U.S.C. §103 as being unpatentable over Liu (US 20210249365 A1) and Hwang(US 20210066123 A1) further in view of Ra (JP 7218020 B2).
Regarding claim 1, Liu discloses 1 a semiconductor device structure, comprising: a through silicon via disposed through a dielectric material (see fig 4, 186 tsv, through 122/120), an interconnection structure (see 128), and a substrate, wherein the through silicon via has a top surface having a first diameter and a portion located in the substrate having a second diameter (see taper in tsv), and the first diameter is substantially greater than the second diameter (wider at top than bottom);
However, Liu does not explicitly disclose an alloy portion surrounding the through silicon via; a barrier layer surrounding the alloy portion; and a liner surrounding the barrier layer, wherein the through silicon via, the alloy portion, the barrier layer, and the liner together have a funnel shaped cross-section.
However, Hwang at least at fig 2c discloses an alloy portion surrounding the through silicon via; a barrier layer surrounding the alloy portion; and a liner surrounding the barrier layer, wherein the through silicon via, the alloy portion, the barrier layer, and the liner together have a funnel shaped cross-section (see fig 2b disclosing alloy layer 520, 510 and 410 being alloy, barrier and liner, all having funnel shape) However, Liu and Hwang do not explicitly disclose an alloy portion surrounding the through silicon via, wherein a thickness of the alloy portion decreases in a direction towards the substrate. However, Ra, at least at fig 3e discloses a narrowing thickness metal liner layer 305 in a TSV, see fig 3e.
Liu, Hwang, and Ra are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Liu, Hwang, and Ra. Liu, Hwang, and Ra may be combined by forming the tsv of Ra with liner layers as disclosed in Hwang and Liu. One having ordinary skill the art would have been motivated to combine Liu and Hwang and Ra in order to ensure electrical separation and facilitate electrical connectivity(see description of step S5).
Regarding claim 2, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 1, wherein the through silicon via comprises Cu, the barrier layer comprises Ti, and the alloy portion comprises Cu/Ti alloy (see paras [0032] and [0033]).
Regarding claim 3, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 1, wherein the alloy portion has a top surface having a first width, and the first width is about three percent to about five percent of a sum of the first width and the first diameter (see fig 2b disclosing taper and varying widths of the liner/alloy layers).
Regarding claim 4, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 1, wherein top surfaces of the liner, the barrier layer, the alloy portion, and the through silicon via have a total diameter, and the total diameter is about 1.15 times to about 2.5 times the second diameter(see fig 2b disclosing taper and varying widths of the liner/alloy layers).
Regarding claim 5, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 1, further comprising a guard ring surrounding the through silicon via (see fig 4, 118).
Regarding claim 6, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 5, wherein the guard ring comprises a plurality of closed-loop structures(see fig 4, 118, are multiple layers/rings).
Regarding claim 7, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 6, wherein the plurality of closed-loop structures comprises: a first closed-loop structure having a first inner edge, a first outer edge (see 118 having at least four outer edges), and a first dimension between the first inner and outer edges(see 118 having at least first outer edges); a second closed-loop structure disposed over the first closed-loop structure(see 118 having at least a second outer edges), wherein the second closed-loop structure has a second inner edge, a second outer edge, and a second dimension between the second inner and outer edges(see 118 having at least four outer edges, see fig 4 disclosing arrangement); and a third closed-loop structure disposed over the second closed-loop structure, wherein the third closed-loop structure has a third inner edge, a third outer edge, and a third dimension between the third inner and outer edges(see 118 having at least third outer edges).
Regarding claim 8, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 7, wherein the first dimension and the third dimension are substantially the same (see fig 4 of Liu disclosing that the first and third dimensions of 118 are the same).
Regarding claim 9, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 8, wherein the second dimension is substantially greater than the first and third dimensions (see fig 4, disclosing the spacing of 128 is greater at the bottom).
Regarding claim 10, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 8, wherein a first distance between opposite sides of the first inner edge is substantially smaller than a second distance between opposite sides of the third inner edge (see fig 4 where the spacing varies according to the tsv taper).
Regarding claim 11, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 7, wherein the first, second, and third dimensions are substantially the same (see fig 4 where spacing of 128 near bottom is substantially similar).
Regarding claim 12, Liu, Hwang, and Ra disclose the semiconductor device structure of claim 11, wherein a first distance between opposite sides of the first inner edge is substantially smaller than a second distance between opposite sides of the second inner edge, which is substantially smaller than a third distance between opposite sides of the third inner edge (see fig 4 where spacing of 128 near bottom tapers).
Claims 18-20 are rejected under 35 U.S.C. §103 as being unpatentable over Liu (US 20210249365 A1) and further in view of Hwang(US 20210066123 A1)
Regarding claim 18, Liu discloses 18 a method, comprising: forming a guard ring in an interconnection structure (see fig 12, disclosing TSV and guard ring), comprising:
depositing a first closed-loop structure (see fig 12, disclosing closed loop structures), wherein the first closed-loop structure has a first outer edge (see 124);
depositing a second closed-loop structure over the first closed-loop structure, wherein the second closed-loop structure has a second outer edge located laterally outward of the first outer edge (see fig 12, 118); and
depositing a third closed-loop structure over the second closed-loop structure, wherein the third closed-loop structure has a third outer edge located laterally outward of the second outer edge (see 194);
forming an opening depositing a through silicon via into the opening (see figs 3-4 disclosing forming the tsv).
However, Liu does not explicitly disclose that in the interconnection structure surrounded by the guard ring, wherein the opening comprises a bottom portion having a first critical dimension, a middle portion having a second critical dimension, and a top portion having a third critical dimension, wherein the first and third critical dimensions are substantially constant, and the second critical dimension varies. However, Hwang at least at fig 2c, discloses (at least at 400 and 500 that there at least two critical dimensions that are the same and that the critical dimensions vary, see fig 2b/c)
Liu and Hwang are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Liu and Hwang. Liu and Hwang may be combined by forming the tsv of Liu with liner layers as disclosed in Hwang. One having ordinary skill the art would have been motivated to combine Liu and Hwang in order to ensure electrical separation (see para [0073]).
Regarding claim 19, Liu and Hwang disclose the method of claim 18, further comprising depositing a liner in the opening and depositing a barrier layer on the liner in the opening, wherein the through silicon via is deposited on the barrier layer (see Hwang, fig 2c, disclosing liner barrier, and tsv).
Regarding claim 20, Liu and Hwang disclose the method of claim 19, further comprising forming an alloy portion between the barrier layer and the through silicon via (see alloy portion 500 in fig 2c of Hwang).
Response to Arguments
Applicants have amended claim 1 to recite additional features. This office action now cites to Ra, disclosing these features. Applicant’s assertions are now moot.
Regarding claim 18, applicant asserts that the closed loop structures are not over each other. However, in fig 12, it is clear that elements 194, 118 and 124 are nested over each other. Applicant’s assertions are not persuasive.
Allowable Subject Matter
Claim 13 was previously indicated to be allowable. Claims 14-17 are allowable for their dependency on claim 13.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EDWARD CHIN/Primary Examiner, Art Unit 2893
Prosecution Insights